CY2DL15110

1:10 Differential LVDS Fanout Buffer with

Selectable Clock Input

Cypress Semiconductor Corporation

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198 Champion Court

•

San Jose

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408-943-2600

Document Number: 001-69398 Rev. *C

Revised March 12, 2012

1:10 Differential LVDS Fanout Buffer with Selectable Clock Input

Features

pairs to distribute to 10 LVDS output pairs

(12-kHz to 20-MHz offset)

Functional Description

The CY2DL15110 is an ultra-low noise, low skew, low

propagation delay 1:10 LVDS fanout buffer targeted to meet the

requirements of high speed clock distribution applications. The

CY2DL15110 can select between two separate LVDS input clock

pairs using the IN_SEL pin. The output enable function allows

the outputs to be asynchronously driven to a high-impedance

state. The device has a fully differential internal architecture that

is optimized to achieve low additive jitter and low skew at

operating frequencies of up to 1.5 GHz.

Q0

Q0#

Q1

Q1#

Q2

Q2#

Q3

Q3#

Q4

Q4#

Q5

Q5#

Q6

Q6#

Q8

Q8#

Q9

Q9#

Q7

Q7#

IN0

IN0#

IN1

IN1#

IN_SEL

OE

Logic Block Diagram

Note

1. Input AC-coupling capacitors are required for voltage-translation applications.