PE64102MLAA-Z datasheet(10/13 Pages) PEREGRINE

Part #	PE64102MLAA-Z

Description	UltraCMOS짰 Digitally Tunable Capacitor (DTC) 100 - 3000 MHz

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Manufacturer	PEREGRINE [Peregrine Semiconductor Corp.]

Direct Link	http://www.peregrine-semi.com

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10 / 13 page

Product Specification

PE64102

Page 10 of 13

Document No. 70-0428-01 │ UltraCMOS® RFIC Solutions

Figure 17. Evaluation Board Layout

101-0700

Evaluation Board

The 101-0700 Evaluation Board (EVB) was

designed for accurate measurement of the DTC

impedance and loss. Two configurations are

available: 1 Port Shunt (J3) and 2 Port Shunt (J4,

J5). Three calibration standards are provided. The

open (J2) and short (J1) standards (104 ps delay)

are used for performing port extensions and

accounting for electrical length and transmission

line loss. The Thru (J9, J10) standard can be used

to estimate PCB transmission line losses for scalar

de-embedding of the 2 Port Shunt configuration (J4,

J5).

The board consists of a 4 layer stack with 2 outer

layers made of Rogers 4350B (εr = 3.48) and 2

inner layers of FR4 (εr = 4.80). The total thickness

of this board is 62 mils (1.57 mm). The inner layers

provide a ground plane for the transmission lines.

Each transmission line is designed using a coplanar

waveguide with ground plane (CPWG) model using

a trace width of 32 mils (0.813 mm), gap of 15 mils

(0.381 mm), and a metal thickness of 1.4 mils

(0.036 mm).

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