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RT9624C Datasheet(PDF) 9 Page - Richtek Technology Corporation |
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RT9624C Datasheet(HTML) 9 Page - Richtek Technology Corporation |
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9 / 13 page  RT9624C 9 DS9624C-00 September 2012 www.richtek.com © Copyright 2012 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Application Information The RT9624C is a high frequency, synchronous rectified, single phase dual MOSFET driver containing Richtek's advanced MOSFET driver technologies. The RT9624C is designed to be able to adapt from normal MOSFET driving applications to high performance CPU VR driving capabilities. Supply Voltage and Power On Reset The RT9624C can be utilized under both VCC = 5V or VCC = 12V applications which may happen in different fields of electronics application circuits. In terms of efficiency, higher VCC equals higher driving voltage of UGATE/LGATE which may result in higher switching loss and lower conduction loss of power MOSFETs. The choice of VCC = 12V or VCC = 5V can be a tradeoff to optimize system efficiency. The RT9624C is designed to drive both high side and low side N-MOSFET through external input PWM control signal. It has power on protection function which held UGATE and LGATE low before the VCC voltage rises to higher than rising threshold voltage. Enable and Disable The RT9624C includes an EN pin for sequence control. When the EN pin rises above the VENH trip point, the RT9624C begins a new initialization and follows the PWM command to control the UGATE and LGATE. When the EN pin falls below the VENL trip point, the RT9624C shuts down and keeps UGATE and LGATE low. Tri-state PWM Input After the initialization, the PWM signal takes the control. The rising PWM signal first forces the LGATE signal to turn low then UGATE signal is allowed to go high just after a non-overlapping time to avoid shoot through current. The falling of PWM signal first forces UGATE to go low. When UGATE and PHASE signal reach a predetermined low level, LGATE signal is allowed to turn high. The PWM signal is acted as “ High” if the signal is above the rising threshold and acted as “ Low” if the signal is below the falling threshold. When PWM signal level enters and remains within the shutdown window, the output drivers are disabled and both MOSFET gates are pulled and held low. If the PWM signal is left floating, the pin will be kept around 1.8V by the internal divider and provide the PWM controller with a recognizable level. Internal Bootstrap Power Switch The RT9624C builds in an internal bootstrap power switch to replace external bootstrap diode, and this can facilitate PCB design and reduce total BOM cost of the system. Hence, no external bootstrap diode is required in real applications. Non-overlap Control To prevent the overlap of the gate drivers during the UGATE pull low and the LGATE pull high, the non-overlap circuit monitors the voltages at the PHASE node and high side gate drive (UGATE-PHASE). When the PWM input signal goes low, UGATE begins to pull low (after propagation delay). Before LGATE is pulled high, the non-overlap protection circuit ensures that the monitored voltages have gone below 1.1V. Once the monitored voltages fall below 1.1V, LGATE begins to turn high. By waiting for the voltages of the PHASE pin and high side gate driver to fall below 1.1V, the non-overlap protection circuit ensures that UGATE is low before LGATE pulls high. Also to prevent the overlap of the gate drivers during LGATE pull low and UGATE pull high, the non-overlap circuit monitors the LGATE voltage. When LGATE goes below 1.1V, UGATE goes high after propagation delay. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. When Vgs1 or Vgs2 is at 12V or 5V, the gate draws the current only for few nano-amperes. Thus once the gate has been driven up to “ ON” level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down 12V (or 5V) rapidly. It is also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. |
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