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RT9379 Datasheet(PDF) 8 Page - Richtek Technology Corporation |
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RT9379 Datasheet(HTML) 8 Page - Richtek Technology Corporation |
8 / 9 page RT9379 8 DS9379-01 April 2011 www.richtek.com the RT9379, The maximum junction temperature is 125 °C. The junction to ambient thermal resistance θJA is layout dependent. For WQFN-16L 2x3 package, the thermal resistance θJA is 90°C/W on the standard JEDEC 51-7 four layers thermal test board. The maximum power dissipation at TA = 25 °C can be calculated by following formula : PD(MAX) = (125 °C − 25°C) / (90°C/W) = 1.111W for WQFN-16L 2x3 package The maximum power dissipation depends on operating ambient temperature for fixed TJ(MAX) and thermal resistance θJA. For RT9379 package, the Figure 1 of derating curve allows the designer to see the effect of rising ambient temperature on the maximum power dissipation allowed. Figure 1. Derating Curve for RT9379 Package 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 0 25 50 75 100 125 Ambient Temperature (°C) Four Layers PCB WQFN-16L 2x3 Figure 2. PCB Layout Guide Battery GND LED4 AGND VOUT LED6 LED5 EN VIN CF PGND C2P 13 12 11 10 14 15 16 1 2 3 4 8 7 6 17 GND 9 5 GND All the traces of LED pins running from chip to LEDs should be wide and short to reduce the parasitic connection resistance. The trace from CF pin to external capacitance should be as short as possible. The traces running from pins to flying capacitor should be short and wide to reduce parasitic resistance and prevent noise radiation. Output capacitor (COUT) should be placed close to VOUT and connected to ground plane to reduce noise coupling from charge pump to LEDs. Input capacitor (CIN) should be placed close to VIN and connected to ground plane. The trace of VIN in the PCB should be placed far away from the sensitive devices or shielded by the ground. Layout Considerations For best performance of the RT9379, the following layout guidelines should be strictly followed : Output Capacitor (COUT) should be placed close to VOUT and connected to ground plane to reduce noise coupling from charge pump to LEDs. All the traces of LED pins running from chip to LED's should be wide and short to reduce the parasitic connection resistance. The trace from CF pin to external capacitance should be as short as possible. Input capacitor (CIN) should be placed close to VIN and connected to ground plane. The trace of VIN in the PCB should be placed far away from the sensitive devices or shielded by the ground. The traces running from pins to flying capacitor should be short and wide to reduce parasitic resistance and prevent noise radiation. |
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