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RT8259PE Datasheet(PDF) 10 Page - Richtek Technology Corporation |
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RT8259PE Datasheet(HTML) 10 Page - Richtek Technology Corporation |
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10 / 13 page  RT8259 10 DS8259-03 March 2011 www.richtek.com Layout Consideration Follow the PCB layout guidelines for optimal performance of RT8259. Keep the traces of the main current paths as short and wide as possible. Put the input capacitor as close as possible to the device pins (VIN and GND). LX node is with high frequency voltage swing and should be kept at small area. Keep sensitive components away from the LX node to prevent stray capacitive noise pick- up. Place the feedback components to the FB pin as close as possible. Connect GND to a ground plane for noise reduction and thermal dissipation. Figure 4. PCB Layout Guide Thermal Considerations For continuous operation, do not exceed the maximum operation junction temperature 125 °C. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : PD(MAX) = (TJ(MAX) − TA) / θJA where TJ(MAX) is the maximum operation junction temperature, TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification of the RT8259, the maximum junction temperature of the die is 125 °C. The junction to ambient thermal resistance θJA is layout dependent. For T/SOT-23-6 package, the thermal resistance θJA is 120°C/W on standard JEDEC 51-7 four- layers thermal test board. The maximum power dissipation at TA = 25 °C can be calculated by following formula : PD(MAX) = (125 °C − 25°C) / (250°C/W) = 0.4W for T/SOT-23-6 packages The maximum power dissipation depends on operating ambient temperature for fixed TJ(MAX) and thermal resistance θJA . For RT8259 packages, the Figure 3 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. Figure 3. Derating Curves for RT8259 Packages BOOT GND FB EN VIN PHASE 4 2 3 5 6 1 VOUT VOUT CB L1 COUT D1 CIN R2 R1 GND 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 025 50 75 100 125 Ambient Temperature (°C) T/SOT-23-6 Single Layer PCB |
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