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FAN7631SJX Datasheet(PDF) 11 Page - Fairchild Semiconductor

Part # FAN7631SJX
Description  Advanced Pulse Frequency Modulation (PFM) Controller for Half-Bridge Resonant Converters
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Manufacturer  FAIRCHILD [Fairchild Semiconductor]
Direct Link  http://www.fairchildsemi.com
Logo FAIRCHILD - Fairchild Semiconductor

FAN7631SJX Datasheet(HTML) 11 Page - Fairchild Semiconductor

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© 2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FAN7631 • 1.0.2
11
Functional Description
1. Internal Oscillator
Figure 29 shows the simplified circuit of internal current-
controlled oscillator and typical circuit configuration for
the RT pin. Internally, the voltage on the RT pin is
regulated at 2V by the V/I converter. The charging /
discharging current for the oscillator capacitor, CT, is
obtained by mirroring the current flowing out of the RT
pin (ICTC). By comparing the capacitor voltage with VTH
and VTL and driving S/R flip-flop with the comparator
outputs, the clock signal is obtained. Thus, the switching
frequency increases as the RT pin current increases.
As can be seen in Figure 29, an opto-coupler transistor is
typically connected to the RT pin through Rmax to
modulate the switching frequency. During an overload
condition, the opto-coupler is fully turned off and ICTC is
solely determined by Rmin, which sets the minimum
frequency. Meanwhile, the maximum switching frequency
is obtained when the opto-coupler is fully turned on.
Considering the typical saturation voltage of opto-
transistor (0.2V), the maximum frequency can be
obtained by Rmax and Rmin as:
min
min
max
min
max
11.6
50
11.6
10.4
() 50
k
fkHz
R
kk
f
kHz
RR



(1)
Figure 29. Current-Controlled Oscillator
2. Gate Driver and Dead Time Programming
The FAN7631 employs a gate drive circuit with high
driving capability (source: 0.5A / sink: 1A) to cover a wide
variety of applications. The two gate drive signals (LO
and HO) are complimentary; each signal has 50% duty
cycle, including the dead time, as shown in Figure 30.
The dead time can be programmed by the resistor, RDT,
as shown in Figure 31. Internally, the voltage on the DT
pin is regulated at 1.4V by the V/I converter and IDT
programs the dead time using RDT. To improve the noise
immunity of the dead time circuit, a sample-and-hold
circuit is internally employed. However, severe noises in
a high-power application can affect the dead time circuit
operation and it is therefore recommended to use a
bypass capacitor of around 10nF in parallel with the RDT.
As a protective measure against abnormal conditions,
such as DT pin short-to-ground and lift open, shunt-
resistor and series resistor RDT,Short and RDT,Open are
internally connected to the DT pin. Even when this pin is
shorted to ground and lifted open, the dead time is
limited to 50ns (short to ground) and 1000ns (lifted
open). Since the internal resistors have relatively large
tolerance, it is recommended to set the dead time
between 150ns and 600ns to minimize the dead time
variation by the internal resistor tolerance.
Figure 30. Gate Driving Signals
0
100
200
300
400
500
600
0
102030405060
Dead time(ns)
Dead time resistor (RDT, KΩ)
Figure 31. Dead Time vs. RDT
3. Soft-Start
Since the voltage gain of the resonant converter is
inversely proportional to the switching frequency, the
soft-start is implemented by sweeping down the
switching frequency from a high initial frequency until the
output voltage is established. The current-steering circuit
connected to SS pin adaptively changes the sinking and
sourcing current of the SS pin to set soft-start time, OLP
shutdown delay, and restart time. As illustrated in Figure
32, the sourcing current, ISS1 (3mA), is enabled at the
beginning of startup, which rapidly raises VSS up to
VSS_START (1.6V). Then the sourcing current is switched to
ISS2 (30µA) and gate drive signals are enabled. Due to
the small value of ISS2, the SS pin voltage slowly rises,
allowing slow decrease of the switching frequency.
To minimize the frequency variation while the output
capacitance of the opto-transistor is charged up, soft-
start is delayed until the CON pin voltage (opto-coupler
transistor voltage) reaches the RT pin voltage. Thus, the
HO Output
Dead Time
time
LO Output


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