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SPXN3020VMM1R Datasheet(PDF) 2 Page - Freescale Semiconductor, Inc |
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SPXN3020VMM1R Datasheet(HTML) 2 Page - Freescale Semiconductor, Inc |
2 / 139 page PXS30 Microcontroller Data Sheet, Rev. 1 Preliminary—Subject to Change Without Notice Introduction Freescale Semiconductor 2 to assist with users’ implementations. See Section 3, Developer support, for more information. 1 Introduction 1.1 Document overview This document describes the features of the family and options available within the family members, and highlights important electrical and physical characteristics of the devices. This document provides electrical specifications, pin assignments, and package diagrams for the PXS30 series of microcontroller units (MCUs). For functional characteristics, see the PXS30 Microcontroller Reference Manual. 1.2 Device comparison Table 1. PXS30 Family Feature Set Features PXS3010 PXS3015 PXS3020 CPU Type 2 × e200z7d (SoR1) in lock-step or decoupled operation Architecture Harvard Execution speed 0–150 MHz (+2% FM) 0–180 MHz (+2% FM) 0–180 MHz (+2% FM) Nominal platform frequency (in 1:1, 1:2, and 1:3 modes) 0–75 MHz (+2% FM) 0–90 MHz (+2% FM) 0–90 MHz (+2% FM) MMU 64 entries (SoR) Instruction set PPC Yes Instruction set VLE Yes Instruction cache 16 KB, 4-way with EDC (SoR) Data cache 16 KB, 4-way with EDC (SoR) MPU Yes (SoR) Buses Core bus 32-bit address, 64-bit data Internal periphery bus 32-bit address, 32-bit data XBAR Master slave ports Yes (SoR) Memory Static RAM (SRAM) 256 KB (ECC) 384 KB (ECC) 512 KB (ECC) Code Flash memory 1MB2 1.5 MB2 2MB2 Data Flash memory 64 KB2 |
Similar Part No. - SPXN3020VMM1R |
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