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ICX279AK Datasheet(PDF) 3 Page - Sony Corporation

Part No. ICX279AK
Description  Diagonal 4.5mm (Type 1/4) CCD Image Sensor for PAL Color Video Cameras
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Maker  SONY [Sony Corporation]
Homepage  http://www.sony.co.jp
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ICX279AK Datasheet(HTML) 3 Page - Sony Corporation

 
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ICX279AK
Bias Conditions
1 V
L
setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used.
2 Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
Item
VDD
VL
φSUB
φRG
Symbol
15.0
1
2
2
Min.
V
Unit
Remarks
Typ.
Max.
14.55
15.45
DC Characteristics
Supply current
Item
IDD
Symbol
4
Min.
Unit
Remarks
Typ.
Max.
mA
6
Clock Voltage Conditions
Readout clock voltage
Vertical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Item
VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,
VVL3, VVL4
V
φV
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
V
φH
VHL
V
φRG
VRGLH – VRGLL
VRGL – VRGLm
V
φSUB
Symbol
14.55
–0.05
–0.2
–8.0
6.3
–0.25
–0.25
3.0
–0.05
3.0
21.0
Min.
15.0
0
0
–7.0
7.0
3.3
0
3.3
22.0
Typ.
15.45
0.05
0.05
–6.5
8.05
0.1
0.1
0.3
0.3
0.3
0.3
5.25
0.05
5.5
0.4
0.5
23.5
Max.
Unit
1
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
Waveform
diagram
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
V
φV = VVHn – VVLn (n = 1 to 4)
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
Input through 0.1µF
capacitance
Low-level coupling
Low-level coupling
Remarks
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V


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