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EP53A7LQ Datasheet(PDF) 15 Page - Enpirion, Inc.

Part No. EP53A7LQ
Description  1000mA Synchronous Buck Regulator with Integrated Inductor
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Maker  ENPIRION [Enpirion, Inc.]
Homepage  http://www.enpirion.com
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EP53A7LQ Datasheet(HTML) 15 Page - Enpirion, Inc.

 
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01543
11/11/2009
Rev:B
EP53A7LQI/EP53A7HQI
©Enpirion 2009 all rights reserved, E&OE
15
www.enpirion.com
VIN
VSense
VS0
VS2
10
μF
4.7uF
VOUT
VOUT
AGND
ENABLE
Ra
Rb
VFB
VS1
PGND
AVIN
PVIN
LLM
100 Ohm
Figure 11: EP53A7LQI using external divider
The output voltage is selected by the following
formula:
()
Rb
Ra
OUT
V
V
+
=
1
6
.
0
Ra must be chosen as 237KΩ to maintain loop
gain. Then Rb is given as:
Ω
=
6
.
0
10
2
.
142
3
OUT
b
V
x
R
VOUT can be programmed over the range of
0.6V to (VIN – 0.5V).
NOTE:
Dynamic Voltage Scaling is not allowed
between internal preset voltages and external
divider.
NOTE:
LLM is not functional when using the
external divider option. Tie the LLM pin to
AGND when using this option.
EP53A7HQI High VID Range
Programming
The EP53A7HQI VOUT settings are optimized
for higher nominal voltages such as those
required to power IO, RF, or IC memory. The
preset voltages range from 1.8V to 3.3V.
There are eight (8) preset output voltage
settings. The EP53A7HQI does not have an
external
divider
option.
As
with
the
EP53A7LQI, the VID pin settings can be
changed while the device is enabled.
Table 3 shows the VS0-VS2 pin logic states for
the EP53A7HQI and the associated output
voltage levels.
A logic “1” indicates a
connection to AVIN or to a “high” logic voltage
level.
A logic “0” indicates a connection to
AGND or to a “low” logic voltage level. These
pins can be either hardwired to AVIN or AGND
or alternatively can be driven by standard logic
levels. Logic levels are defined in the electrical
characteristics table. Any level between the
logic high and logic low is indeterminate.
These pins must not be left floating.
Table 3: EP53A7HQI VID Voltage Select Settings
VS2
VS1
VS0
VOUT
00
0
3.3
00
1
3.0
01
0
2.9
01
1
2.6
10
0
2.5
10
1
2.2
11
0
2.1
11
1
1.8
Input Filter Capacitor
The input filter capacitor requirement is a
4.7µF 0402 or 0603 low ESR MLCC capacitor.
Output Filter Capacitor
The output filter capacitor requirement is a
minimum of 10µF 0805 MLCC.
Ripple
performance can be improved by using 2x10µF
0603 or 2x10µF 0805 MLCC capacitors.
The maximum output filter capacitance next to
the output pins of the device is 60µF low ESR
MLCC capacitance. VOUT has to be sensed at
the last output filter capacitor next to the
EP53A7xQI.
Additional bulk capacitance for decoupling and
bypass can be placed at the load as long as
there is sufficient separation between the VOUT
Sense point and the bulk capacitance. The
separation provides an inductance that isolates
the control loop from the bulk capacitance.
NOTE:
Excess total capacitance on the output
(Output Filter + Bulk) can cause an over-
current condition at startup.
Refer to the
section on Soft-Start for the maximum total
capacitance on the output.
NOTE:
The Input and Output capacitors must
use a X5R or X7R or equivalent dielectric
formulation.
Y5V or equivalent dielectric
formulations lose capacitance with frequency,
bias, and temperature and are not suitable for
switch-mode DC-DC converter filter applications.


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