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EN6337QI3 Datasheet(PDF) 10 Page - Enpirion, Inc. |
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EN6337QI3 Datasheet(HTML) 10 Page - Enpirion, Inc. |
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10 / 17 page  05800 6/17/2011 Rev: B EN6337QI ©Enpirion 2011 all rights reserved, E&OE 10 www.enpirion.com Additional Features: • The switching frequency can be phase- locked to an external clock to eliminate or move beat frequency tones out of band. • Soft-start circuit allowing controlled startup when the converter is initially powered up. The soft start time is programmable with an appropriate choice of soft start capacitor. • Power good circuit indicating the output voltage is greater than 90% of programmed value as long as feedback loop is closed. • To maintain high efficiency at low output current, the device incorporates automatic light load mode operation. Enable Operation The ENABLE pin provides a means to enable normal operation or to shut down the device. When the ENABLE pin is asserted (high) the device will undergo a normal soft start. A logic low on this pin will power the device down in a controlled manner. From the moment ENABLE goes low, there is a fixed lock out time before the output will respond to the ENABLE pin re- asserted (high). This lock out is activated for even very short logic low pulses on the ENABLE pin. See the Electrical Characteristics Table for technical specifications for this pin. LLM/SYNC Pin This is a dual function pin providing LLM Enable and External Clock Synchronization. At static Logic HIGH, device will allow automatic engagement of light load mode. At static logic LOW, the device is forced into PWM only. A clocked input to this pin will synchronize the internal switching frequency – LLM mode is not available if this input is clocked. If this pin is left floating, it will pull to a static logic high, enabling LLM. Frequency Synchronization The switching frequency of the DC/DC converter can be phase-locked to an external clock source to move unwanted beat frequencies out of band. To avail this feature, the clock source should be connected to the LLM/SYNC pin. An activity detector recognizes the presence of an external clock signal and automatically phase-locks the internal oscillator to this external clock. Phase-lock will occur as long as the clock frequency is in the range specified in the Electrical Characteristics Table. For proper operation of the synchronization circuit, the high-level amplitude of the SYNC signal should not be above 2.5V. Please note LLM is not available when synchronizing to an external frequency. Spread Spectrum Mode The external clock frequency may be swept between the limits specified in the Electrical Characteristics Table at repetition rates of up to 10 kHz in order to reduce EMI frequency components. Soft-Start Operation During Soft-start, the output voltage is ramped up gradually upon start-up. The output rise time is controlled by the choice of soft-start capacitor, which is placed between the SS pin (30) and the AGND pin (32). Rise Time: TR ≈ (CSS* 80kΩ) ± 25% During start-up of the converter, the reference voltage to the error amplifier is linearly increased to its final level by an internal current source of approximately 10uA. Typical soft- start rise time is ~1.2mS with SS capacitor value of 15nF. The rise time is measured from when VIN > VUVLOR and ENABLE pin voltage crosses its logic high threshold to when VOUT reaches its programmed value. Please note LLM function is disabled during the soft-start ramp-up time. POK Operation The POK signal is an open drain signal (requires a pull up resistor to VIN or similar voltage) from the converter indicating the output voltage is within the specified range. The POK signal will be logic high (VIN) when the output voltage is above 90% of programmed VOUT. If the output voltage goes below this threshold, the POK signal will be logic low. |
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