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SPXS1010VLQ64R Datasheet(PDF) 10 Page - Freescale Semiconductor, Inc |
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SPXS1010VLQ64R Datasheet(HTML) 10 Page - Freescale Semiconductor, Inc |
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10 / 130 page  Overview PXD10 Microcontroller Data Sheet, Rev. 1 Freescale Semiconductor 10 Additional notes on low power operation: • Fast wake-up using the on-chip 16 MHz internal RC oscillator allows rapid execution from RAM on exit from low power modes • The 16 MHz internal RC oscillator supports low speed code execution and clocking of peripherals when it is selected as the system clock and can also be used as the PLL input clock source to provide fast start-up without the external oscillator delay • PXD10 devices include an internal voltage regulator that includes the following features: — Regulates input to generate all internal supplies — Manages power gating — Low power regulators support operation when in STOP and STANDBY modes to minimize power consumption — Startup on-chip regulators in <50 µs for rapid exit of STOP and STANDBY modes — Low voltage detection on main supply and 1.2 V regulated supplies 1.6.2 e200z0h core processor The e200z0h processor is similar to other processors in the e200zx series but supports only the VLE instruction set and does not include the signal processing extension for DSP applications or a floating point unit. The e200z0h has all the features of the e200z0 plus: • Branch acceleration using Branch Target Buffer (BTB) • Supports independent instruction and data accesses to different memory subsystems, such as SRAM and Flash memory via independent Instruction and Data BIUs The e200z0h processor uses a four stage in-order pipeline for instruction execution. The Instruction Fetch (stage 1), Instruction Decode/Register file Read/Effective Address Calculation (stage 2), Execute/Memory Access (stage 3), and Register Writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. The integer execution unit consists of a 32-bit Arithmetic Unit (AU), a Logic Unit (LU), a 32-bit Barrel shifter (Shifter), a Mask-Insertion Unit (MIU), a Condition Register manipulation Unit (CRU), a Count-Leading-Zeros unit (CLZ), an 8 × 32 Hardware Multiplier array, result feed-forward hardware, and a hardware divider. Most arithmetic and logical operations are executed in a single cycle with the exception of the divide and multiply instructions. A Count-Leading-Zeros unit operates in a single clock cycle. The Instruction Unit contains a PC incrementer and a dedicated Branch Address adder to minimize delays during change of flow operations. Branch target prefetching from the BTB is performed to accelerate certain taken branches. Sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. Branch target prefetching is performed to accelerate taken branches. Prefetched instructions are placed into an instruction buffer capable of holding four instructions. Conditional branches not taken execute in a single clock. Branches with successful target prefetching have an effective execution time of one clock on e200z0h. All other taken branches have an execution time of two clocks. |
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