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PPXD2020VMG116R Datasheet(PDF) 14 Page - Freescale Semiconductor, Inc

Part No. PPXD2020VMG116R
Description  32-bit Power Architecture® Dual Core Microcontrollers for Industrial Networking
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PPXD2020VMG116R Datasheet(HTML) 14 Page - Freescale Semiconductor, Inc

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PXN20 Product Brief, Rev. 1
Features
Freescale Semiconductor
14
Compatibility with I2C bus standard
Multimaster operation
Software-programmable for one of 256 different serial clock frequencies
Software-selectable acknowledge bit
Interrupt-driven, byte-by-byte data transfer
Arbitration-lost interrupt with automatic mode switching from master to slave
Calling address identification interrupt
Start and stop signal generation/detection
Repeated START signal generation
Acknowledge bit generation/detection
Bus-busy detection
2.6.12
Serial Peripheral Interface Module (SPI)
The PXN20 SPI features the following:
Full duplex, synchronous transfers
Master or slave operation
Programmable master bit rates
Programmable clock polarity and phase
End-of-transmission interrupt flag
Programmable transfer baud rate
Programmable data frames from 4 to 16 bits
Up to 24 chip select lines available (6 per SPI module); the number available at any time is
dependent on package and pin multiplexing.
Up to 4 independently configurable transfer types can be configured for each SPI using the clock
and transfer attributes registers
Chip select strobe available as alternate function on one of the chip select pins for de-glitching
FIFOs for buffering up to 4 transfers on the transmit and receive side
General purpose I/O functionality on pins when not used for SPI
Queueing operation possible through use of eDMA
Serialization of selected sources (eMIOS channels and Phantom ports in SIU)
2.6.13
Enhanced Modular Input Output System (Timers - eMIOS200)
The PXN20 family implement a scaled-down version of the eMIOS module:
Supports timed I/O channels with 16-bit counter resolution
Buffered updates
Support for shifted PWM outputs to minimize occurrence of concurrent edges


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