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PPXD2020VMG116R Datasheet(PDF) 12 Page - Freescale Semiconductor, Inc

Part No. PPXD2020VMG116R
Description  32-bit Power Architecture® Dual Core Microcontrollers for Industrial Networking
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

PPXD2020VMG116R Datasheet(HTML) 12 Page - Freescale Semiconductor, Inc

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PXN20 Product Brief, Rev. 1
Freescale Semiconductor
Cross Triggering Unit (CTU)
The CTU features the following:
Collection of 9 bit timers with an exponential prescaler able to generate the trigger event for ADC
9-bit down counters counting from a programmable start value to 0
Different counters associated with different channel groups
Channel group is defined based on PWM channel clock
Different delay value for each eMIOS flag/PIT event
4-bit programmable exponential prescaler
Single cycle delayed trigger output. Trigger output is a combination of 64 input flags/events
connected to different timers in the system
Maskable interrupt generation whenever a trigger output is generated
Event configuration registers dedicated to UC flag/triggering event
Acknowledgement signal to eMIOS for clearing the flag
Synchronization with ADC to avoid collision
Serial Communication Interface Module (UART)
The PXN20 devices include up to two UART modules and support UART Master mode, UART Slave
mode and UART mode. The modules are UART state machine compliant to the UART 1.3 and 2.0 and 2.1
Specifications and handle UART frame transmission and reception without CPU intervention.
The serial communication interface module offers the following:
UART features:
— Full-duplex operation
— Standard non return-to-zero (NRZ) mark/space format
— Data buffers with 4-byte receive, 4-byte transmit
— Configurable word length (8-bit or 9-bit words)
— Error detection and flagging
– Parity, noise and framing errors
— Interrupt driven operation with 4 interrupts sources
— Separate transmitter and receiver CPU interrupt sources
— 16-bit programmable baud-rate modulus counter and 16-bit fractional
— 2 receiver wake-up methods
LIN features:
— Autonomous LIN frame handling
— Message buffer to store identifier and up to eight data bytes
— Supports message length of up to 64 bytes
— Detection and flagging of LIN errors

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