 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
AD7988-1_1208 Datasheet(PDF) 21 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
AD7988-1_1208 Datasheet(HTML) 21 Page - Analog Devices |
|
|
21 / 24 page  Data Sheet AD7988-1/AD7988-5 Rev. C | Page 21 of 24 APPLICATIONS INFORMATION INTERFACING TO BLACKFIN® DSP The AD7988-x can easily connect to a DSP SPI or SPORT. The SPI configuration is straightforward, using the standard SPI interface as shown in Figure 40. AD7988-1/ AD7988-5 SCK SDO CNV SPI_CLK SPI_MISO SPI_MOSI BLACKFIN DSP Figure 40. Typical Connection to Blackfin SPI Interface Similarly, the SPORT interface can be used to interface to this ADC. The SPORT interface has some benefits in that it can use direct memory access (DMA) and provides a lower jitter CNV signal generated from a hardware counter. Some glue logic may be required between SPORT and the AD7988-x interface. The evaluation board for the AD7988-x interfaces directly to the SPORT of the Blackfin-based (ADSP- BF-527) SDP board. The configuration used for the SPORT interface requires the addition of some glue logic as shown in Figure 41. The SCK input to the ADC was gated off when CNV was high to keep the SCK line static while converting the data, thereby ensuring the best integrity of the result. This approach uses an AND gate and a NOT gate for the SCK path. The other logic gates used on the RSCLK and RFS paths are for delay matching purposes and may not be necessary where path lengths are short. This is one approach to using the SPORT interface for this ADC; there may be other solutions equal to this approach. SCK SDO CNV TSCLK DR TFS RFS RSCLK VDRIVE AD7988-1/ AD7988-5 BLACKFIN DSP Figure 41. Evaluation Board Connection to Blackfin Sport Interface LAYOUT Design the printed circuit board (PCB) that houses the AD7988-x so that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7988-x, with all the analog signals on the left side and all the digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die, unless a ground plane under the AD7988-x is used as a shield. Fast switching signals, such as CNV or clocks, should never run near analog signal paths. Avoid crossover of digital and analog signals. Using at least one ground plane is recommended. It can be common or split between the digital and analog section. In the latter case, join the planes underneath the AD7988-x devices. The AD7988-x voltage reference input, REF, has a dynamic input impedance. Decouple REF with minimal parasitic inductances by placing the reference decoupling ceramic capacitor close to, but ideally right up against, the REF and GND pins and connect- ing them with wide, low impedance traces. Finally, decouple the power supplies of the AD7988-x, VDD and VIO, with ceramic capacitors, typically 100 nF, placed close to the AD7988-x and connected using short and wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. An example of a layout following these rules is shown in Figure 42 and Figure 43. EVALUATING THE PERFORMANCE OF THE AD7988-x The evaluation board package for the AD7988-x (EVAL-AD7988- 5SDZ) includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a PC via the EVAL-SDP-CB1Z. AD7988-1/ AD7988-5 Figure 42. Example Layout of the AD7988-x (Top Layer) Figure 43. Example Layout of the AD7988-x (Bottom Layer) |
|
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
