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AD7988-1_1208 Datasheet(PDF) 18 Page - Analog Devices

Part No. AD7988-1_1208
Description  16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP (QFN)
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7988-1_1208 Datasheet(HTML) 18 Page - Analog Devices

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AD7988-1/AD7988-5
Data Sheet
Rev. C | Page 18 of 24
CS MODE, 3-WIRE
This mode is typically used when a single AD7988-x is
connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 34, and the corresponding timing is
given in Figure 35.
With SDI tied to VIO, a rising edge on CNV initiates a conver-
sion, selects the CS mode, and forces SDO to high impedance.
When the conversion is complete, the AD7988-x enters the
acquisition phase and powers down.
When CNV goes low, the MSB is output onto SDO. The remaining
data bits are then clocked by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided that it has an acceptable
hold time. After the 16th SCK falling edge or when CNV goes
high, whichever is earlier, SDO returns to high impedance.
AD7988-1/
AD7988-5
SDO
DATA IN
DIGITAL HOST
CONVERT
CLK
VIO
CNV
SCK
SDI
Figure 34. 3-Wire CS Mode Connection Diagram
tCONV
tCYC
CNV
ACQUISITION
ACQUISITION
tACQ
tSCK
tSCKL
CONVERSION
SCK
SDO
D15
D14
D13
D1
D0
tEN
tHSDO
1
2
3
14
15
16
tDSDO
tDIS
tSCKH
tCNVH
SDI = 1
Figure 35. 3-Wire CS Mode Serial Interface Timing (SDI High)


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