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AD7988-1_1208 Datasheet(PDF) 14 Page - Analog Devices |
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AD7988-1_1208 Datasheet(HTML) 14 Page - Analog Devices |
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14 / 24 page  AD7988-1/AD7988-5 Data Sheet Rev. C | Page 14 of 24 THEORY OF OPERATION COMP SWITCHES CONTROL BUSY OUTPUT CODE CNV CONTROL LOGIC SW+ LSB SW– LSB IN+ REF GND IN– MSB MSB C C 4C 2C 16,384C 32,768C C C 4C 2C 16,384C 32,768C Figure 29. ADC Simplified Schematic CIRCUIT INFORMATION The AD7988-1/AD7988-5 devices are fast, low power, single- supply, precise 16-bit ADCs that use a successive approximation architecture. The AD7988-1 is capable of converting 100,000 samples per second (100 kSPS), whereas the AD7988-5 is capable of a throughput of 500 kSPS, and they power down between conversions. When operating at 10 kSPS, for example, the ADC consumes 70 µW typically, ideal for battery-powered applications. The AD7988-x provides the user with on-chip track-and-hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. The AD7988-x can be interfaced to any 1.8 V to 5 V digital logic family. It is housed in a 10-lead MSOP or a tiny 10-lead LFCSP (QFN) that combines space savings and allows flexible configurations. CONVERTER OPERATION The AD7988-x is a successive approximation ADC based on a charge redistribution DAC. Figure 29 shows the simplified schematic of the ADC. The capacitive DAC consists of two identical arrays of 16 binary weighted capacitors, which are connected to the two comparator inputs. During the acquisition phase, terminals of the array tied to the comparator’s input are connected to GND via SW+ and SW−. All independent switches are connected to the analog inputs. Therefore, the capacitor arrays are used as sampling capacitors and acquire the analog signal on the IN+ and IN− inputs. When the acquisition phase is completed and the CNV input goes high, a conversion phase is initiated. When the conversion phase begins, SW+ and SW− are opened first. The two capacitor arrays are then disconnected from the inputs and connected to the GND input. Therefore, the differential voltage between the IN+ and IN− inputs captured at the end of the acquisition phase are applied to the comparator inputs, causing the comparator to become unbalanced. By switching each element of the capacitor array between GND and REF, the comparator input varies by binary weighted voltage steps (VREF/2, VREF/4 … VREF/65,536). The control logic toggles these switches, starting with the MSB, to bring the comparator back into a balanced condition. After the completion of this process, the part returns to the acquisition phase and the control logic generates the ADC output code. Because the AD7988-x has an on-board conversion clock, the serial clock, SCK, is not required for the conversion process. |
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