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AD7988-1_1208 Datasheet(PDF) 5 Page - Analog Devices

Part No. AD7988-1_1208
Description  16-Bit Lower Power PulSAR ADCs in MSOP/LFCSP (QFN)
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Maker  AD [Analog Devices]
Homepage  http://www.analog.com
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AD7988-1_1208 Datasheet(HTML) 5 Page - Analog Devices

 
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Data Sheet
AD7988-1/AD7988-5
Rev. C | Page 5 of 24
TIMING SPECIFICATIONS
VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, −40°C to +125°C unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
AD7988-1
Throughput Rate
100
kHz
Conversion Time: CNV Rising Edge to Data Available
t
CONV
9.5
μs
Acquisition Time
t
ACQ
500
ns
Time Between Conversions
t
CYC
10
μs
AD7988-5
Throughput Rate
500
kHz
Conversion Time: CNV Rising Edge to Data Available
t
CONV
1.6
μs
Acquisition Time
t
ACQ
400
ns
Time Between Conversions
t
CYC
2
μs
CNV Pulse Width (CS Mode)
t
CNVH
500
ns
SCK Period (CS Mode)
t
SCK
VIO Above 4.5 V
10.5
ns
VIO Above 3 V
12
ns
VIO Above 2.7 V
13
ns
VIO Above 2.3 V
15
ns
SCK Period (Chain Mode)
t
SCK
VIO Above 4.5 V
11.5
ns
VIO Above 3 V
13
ns
VIO Above 2.7 V
14
ns
VIO Above 2.3 V
16
ns
SCK Low Time
t
SCKL
4.5
ns
SCK High Time
t
SCKH
4.5
ns
SCK Falling Edge to Data Remains Valid
t
HSDO
3
ns
SCK Falling Edge to Data Valid Delay
t
DSDO
VIO Above 4.5 V
9.5
ns
VIO Above 3 V
11
ns
VIO Above 2.7 V
12
ns
VIO Above 2.3 V
14
ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
t
EN
VIO Above 3 V
10
ns
VIO Above 2.3V
15
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
t
DIS
20
ns
SDI Valid Setup Time from CNV Rising Edge
t
SSDICNV
5
ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
t
HSDICNV
2
ns
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
t
HSDICNV
0
ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
t
SSCKCNV
5
ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
t
HSCKCNV
5
ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
t
SSDISCK
2
ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
t
HSDISCK
3
ns


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