© 2009 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FAN6300A / FAN6300H • Rev. 1.0.1

11

Current Sensing and PWM Current Limiting

Peak-current-mode control is utilized to regulate output

voltage and provide pulse-by-pulse current limiting. The

switch current is detected by a sense resistor into the CS

pin. The PWM duty cycle is determined by this current-

voltage around 0.85V for output power limit.

Leading-Edge Blanking (LEB)

Each time the power MOFFET switches on, a turn-on

spike occurs on the sense resistor. To avoid premature

termination of the switching pulse, lead-edge blanking time

is built in. During the blanking period, the current limit

comparator is disabled; it cannot switch off the gate driver.

Under-Voltage Lockout (UVLO)

The turn-on, PWM-off, and turn-off thresholds are fixed

internally at 16/10/8V, respectively. During startup, the

startup capacitor must be charged to 16V through the

startup resistor to enable the IC. The hold-up capacitor

must not drop below 10V during this startup process.

This UVLO hysteresis window ensures that hold-up

Gate Output

The BiCMOS output stage is a fast totem-pole gate

driver. Cross conduction has been avoided to minimize

heat dissipation, increase efficiency, and enhance

reliability. The output driver is clamped by an internal

18V Zener diode to protect power MOSFET transistors

against undesired over-voltage gate signals.

Over-Power Compensation

To compensate for the variation of a wide AC input

range, the DET pin produces an offset voltage to

compensate the threshold voltage of the peak current

limit for a constant-power limit. The offset is generated in

accordance with the input voltage when PWM signal is

enabled. This results in a lower current limit at high-line

inputs than low-line inputs. At fixed-load condition, the

also affects the H/L line constant power limit.

6

VDD

DET 1

5

GATE

3

CS

4

GND

ON

Figure 22. H/L Line Constant Power Limit

Compensated by DET Pin

voltage drops below the UVLO, then starts again.

Output Over-Voltage Protection

The output over-voltage protection works by the

sampling voltage, as shown in Figure 23, after switch-off

sequence. A 4μs blanking time ignores the leakage

inductance ringing. A voltage comparator and a 2.5V

reference voltage develop an output OVP protection. The

ratio of the divider determines the sampling voltage of

the stop gate, as an optical coupler and secondary shunt

regulator are used. If the DET pin OVP is triggered, the

power system enters latch-mode until AC power is

removed.

Figure 23. Voltage Sampled After 4μs

Blanking Time After Switch-Off Sequence

Short-Circuit and Open-Loop Protection

The FB voltage increases every time the output of the

power supply is shorted or overloaded. If the FB voltage

of 16V through the startup resistor until PWM output is

restarted. This protection feature continues as long as

the overloading condition persists. This prevents the

power supply from overheating due to overloading.