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F28M35H20B1 Datasheet(PDF) 6 Page - Texas Instruments |
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F28M35H20B1 Datasheet(HTML) 6 Page - Texas Instruments |
6 / 192 page F28M35H20B1, F28M35H20C1 F28M35H22B1, F28M35H22C1, F28M35H32B1, F28M35H32C1 F28M35H50B1, F28M35H50C1, F28M35H52B1, F28M35H52C1 SPRS742D – JUNE 2011 – REVISED AUGUST 2012 www.ti.com LOCATION ADDITIONS, DELETIONS, AND MODIFICATIONS Section 2.4 Control Subsystem: • Updated "The Control Subsystem includes ..." paragraph Figure 2-2 Updated "Control Subsystem" figure Table 2-16 PIE Peripheral Interrupts: • INTx.3, INT12: Changed from "C28FLFSM" to "Reserved" Section 2.4.5 C28x Local Peripherals: • Updated "The C28x local peripherals include an NMI Watchdog ..." paragraph Section 2.4.7 C28x Accessing Shared Resources and Analog Peripherals: • Updated "The Shared Resources ..." paragraph Section 2.5 Analog Subsystem: • Updated "The Analog Subsystem has ADC1 ..." paragraph Section 2.5.1 ADC1: • Updated "The ADC1 consists of a 12-bit Analog-to-Digital converter ..." paragraph Figure 2-3 Updated "Analog Subsystem" figure Section 2.5.4 Analog Common Interface Bus (ACIB): • Updated "The ACIB bus links the Master and Control Subsystems ..." paragraph Section 2.6 Master Subsystem NMIs: • Updated "The inputs to the Cortex™-M3 NMI block include ..." paragraph Section 2.7 Control Subsystem NMIs: • Updated "The inputs to the C28x NMI block include ..." paragraph Figure 2-4 Updated "Cortex™-M3 NMI and C28x NMI" figure Section 2.8 Resets: • Updated "The XRS pin can receive an external reset signal ..." paragraph Figure 2-5 Updated "Resets" figure Section 2.8.3 Analog Subsystem and Shared Resources Resets: • Added "EPI is a shared peripheral ..." paragraph Section 2.8.4 Device Boot Sequence: • Updated "Boot Mode 7 ..." paragraph • Updated "Boot Mode 1 causes the Master boot program to branch ..." paragraph • Updated "Boot Modes 0, 2, 3, ..." paragraph Table 2-17 Master Subsystem Boot Mode Selection: • Added Boot Modes 8–15 • Updated and added footnotes Section 2.9 Added "Internal Voltage Regulation and Monitoring" section Section 2.10 Added "Input Clocks and PLLs" section Figure 2-10 Updated "Cortex™-M3 Clocks and Low-Power Modes" figure Section 2.12 Control Subsystem Clocking: • Updated "The C28x processor outputs two clocks ..." paragraph Figure 2-11 Updated "C28x Clocks and Low-Power Modes" figure Section 2.12.3 C28x Standby Mode: • Updated "In Standby Mode, the C28x processor stops executing instructions ..." paragraph • Added NOTE about GPIO_MUX1 pins PF6_GPIO38 and PG6_GPIO46 Section 2.14 Shared Resources Clocking: • Updated "... are clocked by PLLSYSCLK." paragraph • Added "EPI is a shared peripheral ..." paragraph Section 2.15 Added "Loss of Input Clock (NMI Watchdog Function)" section Section 2.16 GPIOs and Other Pins: • Updated "Most of the I/O pins of the Concerto™ MCU ..." paragraph 6 Contents Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback |
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