 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ICX087AKB Datasheet(PDF) 3 Page - Sony Corporation |
|
||||||||||||||||||||||||||||||
ICX087AKB Datasheet(HTML) 3 Page - Sony Corporation |
|
|
3 / 17 page  – 3 – ICX087AKB Clock Voltage Conditions Item Readout clock voltage VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 V φV VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL V φH VHL V φRG VRGLH – VRGLL VRGH V φSUB 14.55 –0.05 –0.2 –8.0 6.8 –0.25 –0.25 3.0 –0.05 4.5 VDD + 0.3 21.5 15.0 0 0 –7.5 7.5 5.0 0 5.0 VDD + 0.6 22.5 15.45 0.05 0.05 –7.0 8.05 0.1 0.1 0.3 0.3 0.3 0.3 5.25 0.05 5.5 0.8 VDD + 0.9 23.5 V V V V V V V V V V V V V V V V V 1 2 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 VVH = (VVH1 + VVH2) / 2 VVL = (VVL3 + VVL4) / 2 V φV = VVHn – VVLn (n = 1 to 4) High-level coupling High-level coupling Low-level coupling Low-level coupling Input through 0.01µF capacitance Low-level coupling Horizontal transfer clock voltage Reset gate clock voltage Substrate clock voltage Vertical transfer clock voltage Symbol Min. Typ. Max. Unit Waveform diagram Remarks Bias Conditions Item Supply voltage Protective transistor bias Substrate clock VDD VL φSUB 14.55 15.0 ∗1 ∗2 15.45 V Symbol Min. Typ. Max. Unit Remarks DC Characteristics Item Supply current IDD 4 6 mA Symbol Min. Typ. Max. Unit Remarks ∗1 V L setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. ∗2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD. |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
