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WM7230IMSE/V Datasheet(PDF) 6 Page - Wolfson Microelectronics plc |
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WM7230IMSE/V Datasheet(HTML) 6 Page - Wolfson Microelectronics plc |
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6 / 12 page  WM7230 Preliminary Technical Data w PTD, Rev 2.4, October 2012 6 6. SLEEP Mode is enabled when the CLK input is below the CLK Sleep Frequency noted above. This is a power-saving mode. Normal operation resumes automatically when the CLK input is above the CLK Sleep Frequency. Note that the VDD supply is still required in SLEEP mode. AUDIO INTERFACE TIMING tL_EN CLK (input) tL_DIS tR_EN tR_DIS tCY DAT is high-impedance (hi-z) when not outputting data DAT (LRSEL = 1) DAT (LRSEL = 0) Figure 1 Digital Microphone Interface Timing Test Conditions The following timing information is valid across the full range of recommended operating conditions. PARAMETER SYMBOL MIN TYP MAX UNIT Digital Microphone Interface Timing CLK cycle time tCY 308 1000 ns CLK duty cycle 60:40 40:60 DAT enable from rising CLK edge (LRSEL = 1) tL_EN 18 ns DAT disable from falling CLK edge (LRSEL = 1) tL_DIS 16 ns DAT enable from falling CLK edge (LRSEL = 0) tR_EN 18 ns DAT disable from rising CLK edge (LRSEL = 0) tR_DIS 16 ns Notes: 1. The DAT output is high-impedance when not outputting data; this enables the outputs of two microphones to be connected together with the data from one microphone interleaved with the data from the other. (The microphones must be configured to transmit on opposite channels in this case.) 2. In a typical configuration, the Left channel is transmitted following the rising CLK edge (LRSEL = 1). In this case, the Left channel should be sampled by the receiving device on the falling CLK edge, 3. Similarly, the Right channel is typically transmitted following the falling CLK edge (LRSEL = 0). In this case, the Right channel should be sampled by the receiving device on the rising CLK edge. |
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