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WM8912 Datasheet(PDF) 55 Page - Wolfson Microelectronics plc |
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WM8912 Datasheet(HTML) 55 Page - Wolfson Microelectronics plc |
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55 / 128 page  Production Data WM8912 w PD, Rev 4.0, September 2010 55 BCLK FREQUENCY The BCLK frequency is controlled relative to SYSCLK by the BCLK_DIV divider. Internal clock divide and phase control mechanisms ensure that the BCLK and LRCLK edges will occur in a predictable and repeatable position relative to each other and relative to the data for a given combination of DAC sample rate and BCLK_DIV settings. BCLK_DIV is defined in the “Digital Audio Interface Control” section. See also “Clocking and Sample Rates” section for more information. AUDIO DATA FORMATS (NORMAL MODE) In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRCLK transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRCLK transition. Figure 30 Right Justified Audio Interface (assuming n-bit word length) In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition. Figure 31 Left Justified Audio Interface (assuming n-bit word length) In I 2S mode, the MSB is available on the second rising edge of BCLK following a LRCLK transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next. |
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