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FAB1200UCX Datasheet(PDF) 11 Page - Fairchild Semiconductor |
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FAB1200UCX Datasheet(HTML) 11 Page - Fairchild Semiconductor |
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11 / 16 page  © 2010 Fairchild Semiconductor Corporation www.fairchildsemi.com FAB1200 • Rev 1.2.6 11 I2C Control Writing to and reading from the registers is accomplished via the I 2C interface. The I2C protocol requires that one device on the bus initiates and controls all read and write operations. This device is called the “master” device. The master device also generates the SCL signal, which is the clock signal for all other “slave” devices on the bus. The FAB1200 is a slave device. Both the master and slave devices can send and receive data on the bus. During I 2C operations, one data bit is transmitted per clock cycle. All I 2C operations follow a repeating nine- clock-cycle pattern that consists of eight bits (one byte) of transmitted data followed by an acknowledge (ACK) or not acknowledge (NACK) from the receiving device. Note that there are no unused clock cycles during any operation; therefore, there must be no breaks in the stream of data and ACKs/NACKs during data transfers. For most operations, I 2C protocol requires the serial data (SDA) line remain stable (unmoving) whenever serial clock line (SCL) is HIGH: transitions on the SDA line can only occur when SCL is LOW. The exceptions to this rule are when the master device issues a START or STOP condition. The slave device cannot issue a START or STOP condition. START Condition: This condition occurs when the SDA line transitions from HIGH to LOW while SCL is HIGH. The master device uses this condition to indicate that a data transfer is about to begin. STOP Condition: This condition occurs when the SDA line transitions from LOW to HIGH while SCL is HIGH. The master device uses this condition to signal the end of a data transfer. Acknowledge (ACK) and Not Acknowledge (NACK): When data is transferred to the slave device, it sends an acknowledge (ACK) after receiving every byte of data. The receiving device sends an ACK by pulling SDA LOW for one clock cycle. When the master device is reading data from the slave device, the master sends an ACK after receiving every byte of data. Following the last byte, a master device sends a "not acknowledge" (NACK) instead of an ACK, followed by a STOP condition. A NACK is indicated by leaving SDA HIGH during the clock after the last byte. Slave Address Each slave device on the bus has a unique address so the master can identify which device is sending or receiving data. The FAB1200 slave address is 1100000X binary where “X” is the read/write bit. Master write operations are indicated when X=0. Master read operations are indicated when X=1. Writing to and Reading from the FAB1200 All read and write operations must begin with a START condition generated by the master device. After the START condition, the master device must immediately send a slave address (7 bits), followed by a read/write bit. If the slave address matches the address of the FAB1200, the FAB1200 sends an ACK after receiving the read/write bit by pulling the SDA line LOW for one clock cycle. Setting the Pointer For all operations, the pointer stored in the command register must be pointing to the register to be written to or read from. To change the pointer value in the command register, the Read/Write bit following the address must be 0. This indicates that the master will write new information into the Command register. After the FAB1200 sends an ACK in response to receiving the address and Read/Write bit, the master device must transmit an appropriate 8-bit pointer value, as explained in the I 2C Registers section. The FAB1200 sends an ACK after receiving the new pointer data. The pointer set operation is illustrated in Figure 21 and Figure 22. Any time a pointer set is performed, it must be immediately followed by a read or write operation. The Command register retains the current pointer value between operations; therefore, once a register is indicated, subsequent read operations do not require a pointer set cycle. Write operations always require the pointer be reset. Reading If the pointer is already pointing to the desired register, the master can read from that register by setting the Read/Write bit (following the slave address) to 1. After sending an ACK, the FAB1200 begins transmitting data during the following clock cycle. The master should respond with a NACK, followed by a STOP condition (see Figure 19) . The master can read multiple bytes by responding to the data with an ACK instead of a NACK and continuing to send SCL pulses, as shown in Figure 20. The FAB1200 increments the pointer by one and sends the data from the next register. The master indicates the last data byte by responding with a NACK, followed by a STOP. To read from a register other than the one currently indicated by the Command register, a pointer to the desired register must be set. Immediately following the pointer set, the master must perform a REPEAT START condition (see Figure 22), which indicates to the FAB1200 that a new operation is about to occur. If the REPEAT START condition does not occur, the FAB1200 assumes that a write is taking place and the selected register is overwritten by the upcoming data on the data bus. After the START condition, the master must again send the device address and Read/Write bit. This time, the Read/Write bit must be set to 1 to indicate a read. The rest of the read cycle is the same as described in the previous paragraphs for reading from a preset pointer location. |
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