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328209-001EN Datasheet(PDF) 4 Page - Intel Corporation |
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328209-001EN Datasheet(HTML) 4 Page - Intel Corporation |
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4 / 70 page  4 Reference Number: 328209-001EN List of Figures 2-1 Intel® Xeon Phi™ Coprocessor Board Schematic ..................................................... 9 2-2 Intel® Xeon Phi™ Coprocessor Board Top side...................................................... 10 2-3 Intel® Xeon Phi™ Coprocessor Board, Back side ................................................... 11 2-4 Intel® Xeon Phi™ Coprocessor Silicon Layout ....................................................... 12 3-1 Location of Mounting Holes on the Intel® Xeon Phi™ Coprocessor (in mils) .............. 16 3-2 Dimensions of Intel® Xeon Phi™ Coprocessor (dimension in mils) ........................... 17 3-3 Entering and Exiting Thermal Throttling (PROCHOT) .............................................. 19 3-4 Exploded View of 3100 Series Active Solution ....................................................... 20 3-5 Exploded View of Passive Thermal Solution .......................................................... 21 3-6 Airflow Requirement vs. Inlet Temperature for the 5110P/3100 Series Passive Cards . 23 3-7 Airflow Requirement vs. Inlet Temperature for the SE10P Passive Card .................... 24 3-8 Airflow Requirement vs. Inlet Temperature for the 5110P Card with 245W TDP ......... 25 3-9 SE10X Power Profile for Coprocessor Intensive Workload (all values in Watts)........... 26 3-10 SE10X Power Profile for Memory Intensive Workload (all values in Watts)................. 27 3-11 SE10X SKU Coprocessor Junction Temperature (Tjunction) vs Power ....................... 28 3-12 SE10X SKU Coprocessor Case Temperature (Tcase) vs Power ................................. 29 3-13 SE10X Board Top Side....................................................................................... 31 3-14 SE10X Board Bottom Side.................................................................................. 32 3-15 Contents of Intel® Xeon Phi™ Coprocessor Package Shipment................................ 34 3-16 Overlap Lid ...................................................................................................... 34 3-17 Clearance Lid ................................................................................................... 35 3-18 Overlap Lid Removal ......................................................................................... 35 3-19 Tilt Overlap Lid and Slide as shown to Disengage Tabs........................................... 36 3-20 OEM Bracket Installation.................................................................................... 36 3-21 OEM Bracket Installation.................................................................................... 37 3-22 Replace Lid on “Overlap Lid” Units....................................................................... 37 3-23 Replace Lid on “Overlap Lid” Units (cont.) ............................................................ 38 5-1 Coprocessor in C0-state and Memory in M0-state .................................................. 45 5-2 Some cores are in C0-state and other cores in C1-state; Memory in M0-state ........... 45 5-3 All Cores In C1 state; Memory In M1 state ........................................................... 46 5-4 All Cores In Package-C3 State; Memory In M1 ...................................................... 46 5-5 Package-C3 and Memory M2 state....................................................................... 47 5-6 Package-C6 and Memory M2 state....................................................................... 47 5-7 Package-C6 and Memory M3 state....................................................................... 48 5-8 Intel® Xeon Phi™ Coprocessor P-states ............................................................... 49 6-1 Intel® Xeon Phi™ coprocessor System Manageability Architecture........................... 52 6-2 Schematic Representation of PROCHOT_N on the Intel® Xeon Phi™ coprocessor ....... 54 6-2 Example of Using Power Limits ........................................................................... 56 6-3 Write Block Command Diagram .......................................................................... 60 6-4 Read Block Command Diagram ........................................................................... 61 |
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