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ICX059 Datasheet(PDF) 4 Page - Sony Corporation |
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ICX059 Datasheet(HTML) 4 Page - Sony Corporation |
4 / 18 page – 4 – ICX059AK Clock Voltage Conditions Item Readout clock voltage VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 V φV I VVH1 – VVH2 I VVH3 – VVH VVH4 – VVH VVHH VVHL VVLH VVLL V φH,VφLH VHL,VLHL V φRG VRGLH – VRGLL V φSUB 14.55 –0.05 –0.2 –9.0 7.8 –0.25 –0.25 4.75 –0.05 4.5 22.5 15.0 0 0 –8.5 8.5 5.0 0 5.0 23.5 15.45 0.05 0.05 –8.0 9.05 0.1 0.1 0.1 0.5 0.5 0.5 0.5 5.25 0.05 5.5 0.8 24.5 V V V V V V V V V V V V V V V V V 1 2 2 2 2 2 2 2 2 2 2 2 3 3 4 4 5 VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 V φV = VVHn – VVLn (n = 1 to 4) High-level coupling High-level coupling Low-level coupling Low-level coupling ∗5 ∗5 ∗6 Low-level coupling Horizontal transfer clock voltage Reset gate clock voltage Substrate clock voltage Vertical transfer clock voltage Symbol Min. Typ. Max. Unit Waveform diagram Remarks ∗5 The horizontal final stage transfer clock input pin LHφ 1 is connected to the horizontal transfer clock input pin H φ1. ∗6 The reset gate clock voltage need not be adjusted when reset gate clock is driven when the specifications are as given below. In this case, the reset gate clock voltage setting indicated on the back of the image sensor has not significance. Item Symbol VRGL V φRG Min. Typ. Max. Unit Waveform diagram –0.2 8.5 0 9.0 0.2 9.5 V V 4 4 Remarks Reset gate clock voltage |
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