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ISO5500EVM Datasheet(PDF) 4 Page - Texas Instruments |
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ISO5500EVM Datasheet(HTML) 4 Page - Texas Instruments |
4 / 14 page DRAIN GATE SOURCE MFG1 MFG2 P5 VE P6 MFG4 MFG6 MFG3 MFG5 +HV CONNECTED TO P6 OR MFG2 Banana-Jack Banana-Jack Q1 +HV RETURN CONNECTED TO MFG5 LOAD PCB CONNECTIONS +HV D G S SCHEMATIC LOAD DRAIN GATE SOURCE MFG1 MFG2 P5 VE P6 MFG4 MFG6 MFG3 MFG5 +HV CONNECTED TO MFG6 Banana-Jack Banana-Jack Q1 +HV RETURN CONNECTED TO P5 OR MFG1 LOAD PCB CONNECTIONS +HV D G S SCHEMATIC LOAD Printed-Circuit Board www.ti.com Figure 2. High-Side Interconnection Diagram Figure 3. Low-Side Interconnection Diagram 2.1.2.4 Turnon/Turnoff Adjust The PCB contains a single, 10- Ω gate resistor (R4) and a short bus wire in place of diode D2. This simple configuration sets the peak current at approximately 3 A, with turnon/ turnoff characteristics the same. The PCB has provisions for the user to install the D2 and D3 diodes and R4 and R5 resistors. This allows the user to evaluate device operation with different on/off characteristics. This is shown in Figure 4. The turnon characteristics can also be adjusted with the value of R2, which connects VC to VCC2. As shipped, R2 is set to 0 Ω, but the user can change this and examine the effects on turnon characteristics. 4 ISO5500EVM SLLU136 – September 2011 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated |
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