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ICX038DLB Datasheet(PDF) 4 Page - Sony Corporation

Part No. ICX038DLB
Description  Diagonal 8mm (Type 1/2) CCD Image Sensor for EIA Black-and-White Video Cameras
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Maker  SONY [Sony Corporation]
Homepage  http://www.sony.co.jp
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ICX038DLB Datasheet(HTML) 4 Page - Sony Corporation

 
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ICX038DLB
Item
VDD
VRD
VGG
VSS
VL
VDSUB
VSUB
∆VSUB
14.55
14.55
1.75
6.0
–3
15.0
15.0
2.0
∗3
∗4
15.45
15.45
2.25
14.0
+3
V
V
V
V
%
VRD = VDD
∗5
∗5
Symbol
Min.
Typ.
Max.
Unit
Remarks
Bias Conditions 2 [when used in substrate bias external adjustment mode]
Output circuit supply voltage
Reset drain voltage
Output circuit gate voltage
Output circuit source
Protective transistor bias
Substrate bias circuit supply voltage
Substrate voltage adjustment range
Substrate voltage adjustment precision
∗3 V
L
setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used. (When CXD1267AN is used.)
∗4 Connect to GND or leave open.
∗5 The setting value of the substrate voltage (V
SUB
) is indicated on the back of the image sensor by a special
code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated
voltage. The adjustment precision is ±3%. However, this setting value has not significance when used in
substrate bias internal generation mode.
VSUB code — one character indication
Code and optimal setting correspond to each other as follows.
DC Characteristics
Item
Output circuit supply current
IDD
5.0
10.0
mA
Symbol
Min.
Typ.
Max.
Unit
Remarks
VSUB code
Optimal setting 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0
E
f
G
h
J
K
L
m
N
P
Q
R
S
T
U
V
W
<Example> "L"
→ VSUB = 9.0V
Item
VDD
VRD
VGG
VSS
VL
VDSUB
φSUB
14.55
14.55
1.75
14.55
15.0
15.0
2.0
∗1
15.0
∗2
15.45
15.45
2.25
15.45
V
V
V
V
VRD = VDD
Symbol
Min.
Typ.
Max.
Unit
Remarks
Bias Conditions 1 [when used in substrate bias internal generation mode]
Output circuit supply voltage
Reset drain voltage
Output circuit gate voltage
Output circuit source
Protective transistor bias
Substrate bias circuit supply voltage
Substrate clock
Grounded with 390
Ω resistor
∗1 V
L
setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL
power supply for the V driver should be used. (When CXD1267AN is used.)
∗2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
Grounded with 390
Ω resistor


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