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PEC02SAAN Datasheet(PDF) 4 Page - Texas Instruments |
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PEC02SAAN Datasheet(HTML) 4 Page - Texas Instruments |
4 / 17 page Thermal Guidelines and Layout Recommendations www.ti.com 4.2 Output Load Transient Figure 2 shows the V OUT transient response Figure 2. Step Load and Output Voltage Transient Response 5 Thermal Guidelines and Layout Recommendations Thermal management is a key consideration in the design of any dc-dc converter but is especially important for an LDO when the power dissipation is high. Use the equation below to approximate the worst case junction temperature for the application: T J = TA + Pd × θJA (1) where T J is the junction temperature (°C), TA is the ambient temperature (°C), Pd is the power dissipation in the device (Watts), and θ JA is the thermal resistance from junction to ambient (°C/W). The maximum silicon junction temperature should not be allowed to exceed 125°C for reliable operation. The layout design must use copper traces and plane areas smartly, as thermal sinks, so as to not allow T J to exceed the absolute maximum rating under all load, voltage, and temperature conditions for a given application. The layout should consider carefully the thermal design of the PCB for optimal performance over temperature. For this EVM, Figure 4 shows that the RGW package footprint employs a square thermal pad, centered under the part, for conducting heat to the copper spreading layers of the PCB. The thermal pad is soldered directly to a pad on the PCB containing a 5 × 5 pattern of 10.mil vias for conducting heat to the bottom side ground plane copper. Approximately 4.0 in 2 of 2 ounce copper is used on the bottom side of the EVM for dissipating heat generated by the LDO. Table 2 relies on thermal resistance information from the Thermal Information Table of the TPS7A4700 data sheet for comparison with the approximate thermal resistance, θ JA, calculated for this EVM layout to show the variation in junction-ambient thermal resistances for varying copper areas. The High-K thermal resistance, θ JA, is determined using a standard JEDEC high-k (2s2p) board having dimensions of 3 in × 3 in with two 1-ounce internal power and ground planes and one 2-ounce copper bottom plane for spreading/sinking heat from the IC component. Table 2. Thermal Resistance, θ JA, and Maximum Power Dissipation Max Dissipation without Max Dissipation without Board Package θ JA Derating (T A = 25°C) Derating (T A = 70°C) High-K RGW 30.5°C/W 3.27 W 1.8 W TPS7A4700EVM-094 RGW 21°C/W 4.76 W 2.6 W 4 TPS7A4700EVM-094 Evaluation Module SLVU741 – May 2012 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated |
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