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LPC4357JET256 Datasheet(PDF) 4 Page - NXP Semiconductors

Part # LPC4357JET256
Description  Errata sheet LPC435x/3x/2x/1x
Download  11 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC4357JET256 Datasheet(HTML) 4 Page - NXP Semiconductors

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ES_LPC435X_3X_2X_1X
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Errata sheet
Rev. 2 — 20 October 2012
4 of 11
NXP Semiconductors
ES_LPC435x/3x/2x/1x
Errata sheet LPC435x/3x/2x/1x
3.
Functional problems detail
3.1 C_CAN.1: Writes to CAN registers write through to other peripherals
Introduction:
Controller Area Network (CAN) is the definition of a high performance communication
protocol for serial data communication. The C_CAN controller is designed to provide a full
implementation of the CAN protocol according to the CAN Specification Version 2.0B. The
C_CAN controller allows to build powerful local networks with low-cost multiplex wiring by
supporting distributed real-time control with a very high level of security.
Problem:
On the LPC43xx, there is an issue with the C_CAN controller AHB bus address decoding
that applies to both C_CAN controllers. It affects the C_CAN controllers when peripherals
on the same bus are used. Writes to the ADC, DAC, I2C, and I2S peripherals can update
registers in the C_CAN controller. Specifically, writes to I2C0, MCPWM, and I2S can affect
C_CAN1. Writes to I2C1, DAC, ADC0, and ADC1 can affect C_CAN0. The spurious
C_CAN controller writes will occur at the address offset written to the other peripherals on
the same bus. For example, a write to ADC0 CR register which is at offset 0 in the ADC,
will result in the same value being written to the C_CAN0 CNTL register which is at offset
0 in the C_CAN controller. Writes to the C_CAN controller will not affect other peripherals.
Work-around:
Workarounds include: Using a different C_CAN peripheral. Peripherals I2C1, DAC, ADC0,
and ADC1 can be used at the same time as C_CAN1 is active without any interference.
The I2C0, MCPWM, and I2S peripherals can be used at the same time as C_CAN0 is
active without any interference. Another workaround is to gate the register clock to the
CAN peripheral in the CCU. This will prevent any writes to other peripherals from taking
effect in the CAN peripheral. However, gating the CAN clock will prevent the CAN
peripheral from operating and transmitting or receiving messages. This workaround is
most useful if your application is modal and can switch between different modes such as
an I2S mode and a CAN mode. Another workaround is to avoid writes to the peripherals
while CAN is active. For example, the ADC could be configured to sample continuously or
when triggered by a timer, before the CAN is configured. Afterwards, C_CAN0 can be
used since the ADC will operate without requiring additional writes.


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