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502R29W151KV3E-SC Datasheet(PDF) 8 Page - Analog Devices |
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502R29W151KV3E-SC Datasheet(HTML) 8 Page - Analog Devices |
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8 / 20 page  AN-1109 Application Note Rev. 0 | Page 8 of 20 where a large amount of board area is available, or where reinforced insulation is required. EDGE GUARDING Noise on the power and ground planes that reaches the edge of a circuit board can radiate as shown in Figure 2 and Figure 3. If the edge is treated with a shielding structure, the noise is reflected back into the interplane space (see “Minimizing EMI Caused by Radially Propagating Waves Inside High Speed Digital Logic PCBs” in the References section). This can increase the voltage noise on the planes, but it can also reduce edge radiation. Making a solid conductive edge treatment on a PCB is possible, but the process is expensive. A less expensive solution that works well is to treat the edges of the board with a guard ring structure laced together by vias. The structure is shown in Figure 9 for a typical 4-layer board. Figure 10 shows how this structure is implemented on the power and ground layers of the primary side of a circuit board. GROUND GROUND VIA EDGE FENCE AND GUARD RINGS POWER Figure 9. Via Fence Structure, Side View Figure 10. Via Fence and Guard Ring, Shown on the Primary Power Plane Layers There are two goals in creating edge guarding. The first goal is to reflect cylindrical emissions from vias back into the interplane space, not allowing it to escape from the edge. The second goal is to shield any edge currents flowing on internal planes due to noise or large currents flowing on traces. The spacing of the vias used to create the edge guard is difficult to determine without extensive modeling. Analog Devices, Inc., test boards used 4 mm via spacing for their evaluation boards. This spacing is small enough to provide attenuation to signals less than 18 GHz INTERPLANE CAPACITANCE Interplane capacitance bypassing is a technique intended to reduce both the conducted and radiated emissions of the board by improving the bypass integrity at high frequencies. This has two beneficial effects. First, it reduces the distance that high frequency noise can spread in the ground and power plane pair. Second, it reduces the initial noise injected into the power and ground planes by providing a bypass capacitance that is effective between 300 MHz and 1 GHz (see PCB Design for Real-World EMI Control in the References section). Power and ground noise reduction provides a better operating environment for noise sensitive components near the iCoupler isolator. Both conducted and radiated emissions are reduced proportionate to the reduction in power and ground noise. The reduction in radiated emissions is not as significant as that achieved with the stitching or edge guarding techniques; however, it significantly improves the power environment of the board. The stack-up used for EMI test boards was signal-ground- power-signal, as shown in Figure 11. A thin core layer is used for the power and ground planes. These tightly coupled planes provide the interplane capacitance layer that supplements the bypass capacitors required for proper operation of the isolator. GROUND POWER SIGNAL/POWER BURIED CAPACITOR LAYER SIGNAL/GROUND Figure 11. PCB Stack-Up for Interplane Capacitance In addition to the ground and power planes, the capacitance can be increased even further by filling signal layers with alternating ground and power fill. The top and bottom layers in Figure 11 are labeled signal/power and signal/ground to illustrate the fills on those particular layers. These fills have the added benefit of creating additional shielding for EMI that leaks around the edges of a via fence structure, keeping it in the PCB. Care should be taken when making ground and power fills. Fills should be tied back to the full reference plane, because a floating fill can act as a patch antenna and radiate instead of shielding. Some recommended practices for fills include • Fills should be tied to their appropriate reference plane along the edges with vias, every 10 mm. • Thin fingers of fill should be removed. • If the fill has an irregular shape, put vias at the extreme edges of the shape. POWER FILL GROUNDED VIA FENCE VIA TO REFERENCE PLANE AVOID SMALL FILL ISLANDS Figure 12. Features of Fill The effectiveness of interplane capacitance is shown in Figure 13. It shows the noise generated on the VDD supply by the encode pulses in an ADuM140x series part. In the top section, it shows r |
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