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CXP913P048 Datasheet(PDF) 22 Page - Sony Corporation |
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CXP913P048 Datasheet(HTML) 22 Page - Sony Corporation |
22 / 26 page – 22 – CXP913P048 VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% VDD = 5.0V ± 10% VDD = 3.0V ± 10% (6) Other (Ta = –20 to +75°C, VSS = 0V reference) Item tCFH, tCFL tDFH, tDFL tDPW tDPR tRFH, tRFL tEIH, tEIL tPIH, tPIL tPMW tPMR tTLH tTHL CFG DFG DPG DPG RFG0 RFG1 EXI0 EXI1 PMI PMSK PMSK ns ns ns ns ns ns ns ns ns ns Symbol Pin Min. 50 100 20 40 Typ. 100 280 40 80 Max. Unit Conditions tsys +200 tsys +200 1000/fc +200 1000/fc +200 50 50 50 50 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 tsys +200 Note) tsys indicates the three values below according to the upper two bits (CPU clock selected) of the clock control register (CLC: 0002FEh). tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11") CFG input high, low level width DFG input high, low level width DPG minimum pulse width DPG minimum removal time RFG input high, low level width EXI input high, low level width PMI input high, low level width PMSK minimum pulse width PMSK minimum removal time XOUT output rise time, fall time When the load is 50pF When tsys = 2000/fc XOUT |
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