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MAX11359A Datasheet(PDF) 12 Page - Maxim Integrated Products |
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MAX11359A Datasheet(HTML) 12 Page - Maxim Integrated Products |
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12 / 67 page  MAX11359A 16-Bit Data-Acquisition System with ADC, DAC, UPIOs, RTC, Voltage Monitors, and Temp Sensor 12 Maxim Integrated TIMING CHARACTERISTICS (Figures 1 and 20) (VAVDD = VAVDD = +1.8V to +3.6V, external VREF = +1.25V, CLK32K = 32.768kHz (external clock), CREG = 10µF, CCPOUT = 10µF, 10µF between CF+ and CF-, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25 °C.) (Note 1) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS SCLK Operating Frequency fSCLK 0 10 MHz SCLK Cycle Time tCYC 100 ns SCLK Pulse-Width High tCH 40 ns SCLK Pulse-Width Low tCL 40 ns DIN to SCLK Setup tDS 30 ns DIN to SCLK Hold tDH 0ns SCLK Fall to DOUT Valid tDO CL = 50pF, Figure 2 40 ns CS Fall to Output Enable tDV CL = 50pF, Figure 2 48 ns CS Rise to DOUT Disable tTR CL = 50pF, Figure 2 48 ns CS to SCLK Rise Setup tCSS 20 ns CS to SCLK Rise Hold tCSH 0ns DVDD Monitor Timeout Period tDSLP (Note 16) 1.5 s Wake-Up (WU) Pulse Width tWU Minimum pulse width required to detect a wake-up event 1µs Shutdown Delay tDPU The delay for SHDN to go high after a valid wake-up event 1µs The turn-on time for the high-frequency clock and FLL (FLLE = 1) (Note 17) 10 ms HFCK Turn-On Time tDFON If FLLE = 0, the turn-on time for the high- frequency clock (Note 18) 10 µs CRDY to INT Delay tDFI The delay for CRDY to go low after the HFCK clock output has been enabled (Note 19) 7.82 ms HFCK Disable Delay tDFOF The delay after a shutdown command has asserted and before HFCK is disabled (Note 20) 1.95 ms SHDN Assertion Delay tDPD (Note 21) 2.93 ms Note 16: The delay for the sleep voltage monitor output, RESET, to go high after VDD rises above the reset threshold. This is largely driven by the startup of the 32kHz oscillator. Note 17: It is gated by an AND function with three inputs—the external RESET signal, the internal DVDD monitor output, and the external SHDN signal. The time delay is timed from the internal LOVDD going high or the external RESET going high, whichever happens later. HFCK always starts in the low state. Note 18: If FLLE = 0, the internal signal CRDY is not generated by the FLL block and INT or INT are deasserted. Note 19: CRDY is used as an interrupt signal to inform the µC that the high-frequency clock has started. Only valid if FLLE = 1. Note 20: tDFOF gives the µC time to clean up and go into sleep-override mode properly. Note 21: tDPD is greater than the HFCK delay for the MAX11358B/MAX11359A to clean up before losing power. |
Similar Part No. - MAX11359A_12 |
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Similar Description - MAX11359A_12 |
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