CY7C1613KV18, CY7C1615KV18

Document Number: 001-44273 Rev. *H

Page 9 of 32

Truth Table

The truth table for CY7C1613KV18, and CY7C1615KV18 follows: [2, 3, 4, 5, 6, 7]

Operation

K

RPS WPS

DQ

DQ

DQ

DQ

Write cycle:

Load address on the rising

edge of K; input write data

on two consecutive K and

K rising edges.

L–H

H [8] L [9] D(A) at K(t + 1)

 D(A + 1) at K(t + 1) D(A + 2) at K(t + 2) D(A + 3) at K(t + 2)

Read cycle:

Load address on the rising

edge of K; wait one and a

half cycle; read data on

two consecutive C and C

rising edges.

L–H

L [9]

X

Q(A) at C(t + 1)

 Q(A + 1) at C(t + 2) Q(A + 2) at C(t + 2) Q(A + 3) at C(t + 3)

NOP: No operation

L–H

H

H

D = X

Q = High Z

D = X

Q = High Z

D = X

Q = High Z

D = X

Q = High Z

Standby: Clock stopped

Stopped

X

X

Previous state

Previous state

Previous state

Previous state

Notes

2. X = “Don't Care,” H = Logic HIGH, L = Logic LOW,

3. Device powers up deselected with the outputs in a tri-state condition.

4. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.

5. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.

6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.

7. Ensure that when clock is stopped K = K and C = C = HIGH. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

8. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.

9. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the

second read or write request.