CY7C1268KV18, CY7C1270KV18

Document Number: 001-57835 Rev. *F

Page 5 of 28

Pin Definitions

Pin Name

I/O

Pin Description

Input output-

synchronous

Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write

operations. These pins drive out the requested data when the read operation is active. Valid data is

driven out on the rising edge of both the K and K clocks during read operations. When read access is

CY7C1268KV18

CY7C1270KV18

LD

Input-

synchronous

Synchronous load. Sampled on the rising edge of the K clock. This input is brought LOW when a bus

cycle sequence is defined. This definition includes address and read/write direction. All transactions

operate on a burst of 2 data. LD must meet the setup and hold times around edge of K.

Input-

synchronous

Byte write select 0, 1, 2, and 3

 active LOW. Sampled on the rising edge of the K and K clocks during

write operations. Used to select which byte is written into the device during the current portion of the

write operations. Bytes not written remain unaltered.

CY7C1268KV18

CY7C1270KV18

All the byte write selects are sampled on the same edge as the data. Deselecting a byte write select

ignores the corresponding byte of data and it is not written into the device.

A

Input-

synchronous

Address inputs. Sampled on the rising edge of the K clock during active read and write operations.

These address inputs are multiplexed for both read and write operations. Internally, the device is

organized as 2 M × 18 (2 arrays each of 1 M × 18) for CY7C1268KV18, and 1 M × 36 (2 arrays each of

512 K × 36) for CY7C1270KV18.

R/W

Input-

synchronous

Synchronous read or write input. When LD is LOW, this input designates the access type (read when

R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times

around edge of K.

QVLD

Valid output

indicator

Valid output indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.

K

Input clock

Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device

K

Input clock

Negative input clock input. K is used to capture synchronous data being presented to the device and

CQ

Echo clock

Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock

(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 22.

CQ

Echo clock

Synchronous echo clock outputs. This is a free running clock and is synchronized to the input clock

(K) of the DDR II+. The timing for the echo clocks is shown in the Switching Characteristics on page 22.

ZQ

Input

Output impedance matching input. This input is used to tune the device outputs to the system data

enables the minimum impedance mode. This pin cannot be connected directly to GND or left

unconnected.

DOFF

Input

PLL turn off

 active LOW. Connecting this pin to ground turns off the PLL inside the device. The timing

in the PLL turned off operation differs from those listed in this data sheet. For normal operation, this pin

can be connected to a pull-up through a 10 k

 or less pull-up resistor. The device behaves in DDR I

mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to

167 MHz with DDR I timing.