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CXP83621 Datasheet(PDF) 9 Page - Sony Corporation |
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CXP83621 Datasheet(HTML) 9 Page - Sony Corporation |
9 / 30 page – 9 – CXP83620/83624, CXP83621/83625 Pull-up resistor "0" after a reset RD (Port B) ∗ "0" after a reset Internal data bus Port B data Port B direction IP Serial data output ebable Port B function select "0" after a reset SO "0" after a reset ∗ Pull-up transistor approx. 100k Ω (VDD = 4.5 to 5.5V) approx. 150k Ω (VDD = 2.7 to 3.3V) Output buffer capability Port B Port C 2 pins Hi-Z Hi-Z After a reset PB2/SCK0 PB5/SCK1 PB4/SO0 PB7/SO1 2 pins Hi-Z PC0 to PC7 8 pins Pull-up resistor "0" after a reset RD (Port B) ∗ "0" after a reset Schmitt input SCK in Internal data bus Port B data Port B direction IP Serial clock output ebable Port B function select "0" after a reset SCK out "0" after a reset ∗ Pull-up transistor approx. 100k Ω (VDD = 4.5 to 5.5V) approx. 150k Ω (VDD = 2.7 to 3.3V) Output buffer capability Port B Pin Circuit format IP Pull-up resistor Port C data Port C direction "0" after a reset RD (Port C) "0" after a reset ∗2 Internal data bus ∗1 ∗2 Pull-up transistor approx. 100k Ω (VDD = 4.5 to 5.5V) approx. 150k Ω (VDD = 2.7 to 3.3V) ∗1 High current drive 12mA (VDD = 4.5 to 5.5V) 4.5mA (VDD = 2.7 to 3.3V) |
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Similar Description - CXP83621 |
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