SPEAR320 datasheet(7/73 Pages) STMICROELECTRONICS

Part #	SPEAR320

Description	Embedded MPU with ARM926 core, optimized for factory automation and consumer applications

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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7 / 73 page

SPEAr320

List of figures

Doc ID 16755 Rev 5

7/73

List of figures

Figure 1.

Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8

Figure 2.

Typical system architecture using SPEAr320 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 3.

Hierarchical multiplexing scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 4.

Power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 5.

Power-down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 6.

DDR2 read cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 7.

DDR2 write cycle waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 8.

DDR2 command waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 9.

CLCD waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 10.

Output signal waveforms for I2C signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 11.

Output command signal waveforms for NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 12.

Output address signal waveforms for NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 13.

In/out data address signal waveforms for NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 14.

EMI read cycle waveforms with acknowledgement on EMI_WAIT# . . . . . . . . . . . . . . . . . . 57

Figure 15.

EMI write cycle waveforms with acknowledgement on EMI_WAIT#. . . . . . . . . . . . . . . . . . 57

Figure 16.

EMI read cycle waveforms without acknowledgement on EMI_WAIT# . . . . . . . . . . . . . . . 58

Figure 17.

EMI write cycle waveforms without acknowledgement on EMI_WAIT# . . . . . . . . . . . . . . . 58

Figure 18.

SDIO timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 19.

MII TX waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 20.

MII RX waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 21.

MDC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 22.

SMII input/output timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 23.

SMI I/O waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 24.

SSP_CLK timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 25.

SPI master mode external timing (clock phase = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 26.

SPI master mode external timing (clock phase = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Figure 27.

UART transmit and receive timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 28.

LFBGA289 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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