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CXL5505M Datasheet(PDF) 2 Page - Sony Corporation

Part No. CXL5505M
Description  CMOS-CCD 1H Delay Line for PAL
Download  9 Pages
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Maker  SONY [Sony Corporation]
Homepage  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXL5505M Datasheet(HTML) 2 Page - Sony Corporation

  CXL5505M Datasheet HTML 1Page - Sony Corporation CXL5505M Datasheet HTML 2Page - Sony Corporation CXL5505M Datasheet HTML 3Page - Sony Corporation CXL5505M Datasheet HTML 4Page - Sony Corporation CXL5505M Datasheet HTML 5Page - Sony Corporation CXL5505M Datasheet HTML 6Page - Sony Corporation CXL5505M Datasheet HTML 7Page - Sony Corporation CXL5505M Datasheet HTML 8Page - Sony Corporation CXL5505M Datasheet HTML 9Page - Sony Corporation  
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CXL5505M/P
∗ Description of Pin 3 (VG2)
Control of input signal clamp condition
0V ........ Sync tip clamp condition
5V ........ Center bias condition
Center biased to approx. 2.1V by means of the IC internal resistance (approx. 10k
Ω).
In this mode, the input signal is limited to APL 50% and the maximum input signal amplitude is
200mVp-p.
Clamp
level
Input waveform
Output waveform
Pin Description
Pin No.
Symbol
Description
Impedance
1
2
3∗
4
5
6
7
8
9
10
11
12
13
14
IN
VG1
VG2
OUT
VSS
VSS
VCO OUT
CLK
VDD
PC OUT
VCO IN
VDD
AB
VSS
Signal input
Gate bias 1 DC output
Gate bias 2 DC input
Signal output
GND
GND
VCO output
Clock input
Power supply (5V)
Phase comparator output
VCO input
Power supply (5V)
Auto-bias DC output
GND (SUB)
> 10k
Ω at no clamp
40 to 500
> 10k
600 to 200k
I
O
I
O
O
I
O
I
O
I/O


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