CMOS-CCD 1H Delay Line for NTSC

Description

The CXL5502M/N/P are CMOS-CCD delay line ICs

that provide 1H delay time for NTSC signals including

the external low-pass filter.

The ICs contain a PLL circuit (quadruple progression).

Features

• Single power supply (5V)

• Low power consumption 95mW (Typ.)

• Built-in peripheral circuits

• Clamp level of I/O signal can be selected

• Built-in quadruple PLL circuit

Functions

• 905-bit CCD register

• Clock driver

• Autobias circuit

• Input clamp circuit

• Sample and hold circuit

• PLL circuit (quadruple progression)

Structure

CMOS-CCD

Absolute Maximum Ratings (Ta = 25°C)

• Supply voltage

6V

• Operating temperature Topr

–10 to +60

°C

• Storage temperature

Tstg

–55 to +150

°C

• Allowable power dissipation

CXL5502M

400

mW

CXL5502N

260

mW

CXL5502P

800

mW

Recommended Operating Condition (Ta = 25°C)

Supply voltage

5 ± 5%

V

Recommended Clock Conditions (Ta = 25°C)

• Input clock amplitude

0.3 to 1.0

Vp-p

(0.5Vp-p typ.)

• Clock frequency

3.579545

MHz

• Input clock waveform

Sine wave

Input Signal Amplitude

500mVp-p (Typ.), 572mVp-p (Max.)

(at internal clamp condition)

– 1 –

E89930E79-PS

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by

any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the

operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

CXL5502M/N/P

CXL5502M

14 pin SOP (Plastic)

CXL5502N

16 pin SSOP (Plastic)

CXL5502P

14 pin DIP (Plastic)

For the availability of this product, please contact the sales office.