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CXL1512M Datasheet(PDF) 2 Page - Sony Corporation

Part No. CXL1512M
Description  CCD Delay Line for NTSC
Download  13 Pages
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Manufacturer  SONY [Sony Corporation]
Direct Link  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXL1512M Datasheet(HTML) 2 Page - Sony Corporation

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CXL1512M
Recommended Clock Conditions (Ta = 25*C)
• Input clock amplitude
VCLK
0.3Vp-p to 1.0Vp-p (0.5Vp-p Typ.)
• Clock frequency
fCLK
3.579545MHz
• Input clock waveform
sine wave
Input Signal Amplitude
Vsig
350mVp-p (Typ.), 575mVp-p (Max.)
Block Diagram and Pin Configuration (Top View)
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
Bias circuit
Bias circuit
Clamp circuit
1H
Output
circuit (S/H)
PLL
Timing
Driver
Driver
Output
circuit (S/H)
Autobias
circuit (C)
1H + D
D
fsc buffer
φ1
φ2
Autobias
circuit (Y)


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