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CXK77V3211Q Datasheet(PDF) 5 Page - Sony Corporation

Part No. CXK77V3211Q
Description  32768-word by 32-bit High Speed Synchronous Static RAM
Download  18 Pages
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Manufacturer  SONY [Sony Corporation]
Direct Link  http://www.sony.co.jp
Logo SONY - Sony Corporation

CXK77V3211Q Datasheet(HTML) 5 Page - Sony Corporation

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CXK77V3211Q
Interleaved Burst Sequence Table
First access, latch external address
Second access (first burst address)
Third access (second burst address)
Fourth access (third burst address)
A14 to A2
A14 to A2
latched A14 to A2
latched A14 to A2
latched A14 to A2
A1
A1
latched A1
latched A1
latched A1
A0
A0
latched A0
latched A0
latched A0
Operation
X...X00
X...X01
X...X10
X...X11
First address
X...X01
X...X00
X...X11
X...X10
Second address
X...X10
X...X11
X...X00
X...X01
Third address
X...X11
X...X10
X...X01
X...X00
Fourth address
Address used
Interleaved Burst Address Table
X...X00
X...X01
X...X10
X...X11
First address
Initial WRITE cycle, all bytes
Address = A (n – 1),
data = D (n – 1)
Initial WRITE cycle, all bytes
Address = A (n – 1),
data = D (n – 1)
Initial WRITE cycle, all bytes
Address = A (n – 1),
data = D (n – 1)
Initial WRITE cycle, one byte
Address = A (n – 1),
data = D (n – 1)
All L
All L
All L
One L
Initial READ cycle
Register A (n), Q = D (n – 1)
No new cycle
Q = D (n – 1)
No new cycle
Q = HIGH-Z
No new cycle
Q = D (n – 1) for one byte
L
H
H
H
H
H
H
H
L
L
H
L
Read D (n)
No carryover from
previous cycle
No carryover from
previous cycle
No carryover from
previous cycle
Operation
BWs
Operation
CE
BWs
OE
Operation
Previous cycle
Present cycle
Next cycle
X...X01
X...X10
X...X11
X...X00
Second address
X...X10
X...X11
X...X00
X...X01
Third address
X...X11
X...X00
X...X01
X...X10
Fourth address
Linear Burst Address Table
Pass-Through Truth Table
Note) Previous cycle may be either BURST or NONBURST cycle.


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