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PS21963-4ES Datasheet(PDF) 8 Page - Mitsubishi Electric Semiconductor

Part # PS21963-4ES
Description  Dual-In-Line Package Intelligent Power Module
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

PS21963-4ES Datasheet(HTML) 8 Page - Mitsubishi Electric Semiconductor

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MITSUBISHI SEMICONDUCTOR <Dual-In-Line Package Intelligent Power Module>
PS21963-4ES
TRANSFER-MOLD TYPE
INSULATED TYPE
Mar. 2007
8
Bootstrap negative electrodes
should be connected to U, V,
W terminals directly and
separated from the main output
wires.
WOUT
VOUT
DIP-IPM
C3
C2
C2
C1
C1
C2 C1
UOUT
WP
VWB
VP
VVB
15V line
5V line
UP
COM
UOUT
VOUT
VNO
WOUT
CIN
GND
F
o
WN
VN
VCC
C
A
CIN
NW
NV
NU
W
V
U
P
VWS
VVS
VUS
VUB
VCC
Fo
WN
VN
UN
UN
WP
VP
UP
VNC
VNC
VN1
VP1
VUFB
VVFB
VWFB
C3
HVIC
LVIC
M
Long wiring here might
cause short-circuit.
Long wiring here might cause
SC level fluctuation and
malfunction.
Long GND wiring here might
generate noise to input and
cause IGBT malfunction.
Comparator
C4
R1
B
Vref
C4
R1
B
Vref
C4
N1
R1
B
Vref
OR Logic
External protection circuit
Shunt resistors
-
+
-
+
-
+
Note 1 : Input drive is High-Active type. There is a 3.3kΩ(min.) pull-down resistor integrated in the IC input circuit. To prevent malfunction, the wiring of each in-
put should be as short as possible. When using RC coupling circuit, make sure the input signal level meet the turn-on and turn-off threshold voltage.
2: Thanks to HVIC inside the module, direct coupling to MCU without any opto-coupler or transformer isolation is possible.
3: FO output is open drain type. It should be pulled up to the positive side of a 5V power supply by a resistor of about 10kΩ.
4: To prevent erroneous protection, the wiring of A, B, C should be as short as possible.
5: The time constant R1C4 of the protection circuit should be selected in the range of 1.5-2µs. SC interrupting time might vary with the
wiring pattern. Tight tolerance, temp-compensated type is recommended for R1, C4.
6: All capacitors should be mounted as close to the terminals of the DIP-IPM as possible. (C1: good temperature, frequency character-
istic electrolytic type, and C2, C3: good temperature, frequency and DC bias characteristic ceramic type are recommended.)
7: To prevent surge destruction, the wiring between the smoothing capacitor and the P, N1 terminals should be as short as possible.
Generally a 0.1-0.22µF snubber between the P-N1 terminals is recommended.
8: Two VNC terminals (9 & 16 pin) are connected inside DIP-IPM, please connect either one to the 15V power supply GND outside and
leave another one open.
9: It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction.
10 : If control GND is connected to power GND by broad pattern, it may cause malfunction by power GND fluctuation. It is recommended
to connect control GND and power GND at only a point.
11 : The reference voltage Vref of comparator should be set up the same rating of short circuit trip level (Vsc(ref): min.0.43V to max.0.53V).
12 : OR logic output high level should exceed the maximum short circuit trip level (Vsc(ref): max.0.53V).
Fig. 6 AN EXAMPLE OF TYPICAL DIP-IPM APPLICATION CIRCUIT
C1: Electrolytic capacitor with good temperature characteristics
C2,C3: 0.22~2µF R-category ceramic capacitor for noise filtering


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