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CXK5V81000ATM Datasheet(PDF) 8 Page - Sony Corporation |
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CXK5V81000ATM Datasheet(HTML) 8 Page - Sony Corporation |
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– 8 – CXK5V81000ATM Address OE tWC tAW Data valid tCW tWR1 tWP tDW tDH High impedance CE1 WE Data out Data in tAS tCW ( ∗3) CE2 ∗1 Write is executed when both CE1 and WE are at low and CE2 is at high simultaneously. ∗2 Do not apply the data input voltage of the opposite phase to the output while I/O pin is in output condition. ∗3 tWR1 is tested from either the rising edge of CE1 or the falling edge of CE2, whichever comes earlier, until the end of the write cycle. • Write cycle (3) : CE2 control |
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