AN725 datasheet(9/28 Pages) SILABS

Part #	AN725

Description	ADVANCED LOW POWER TECHNIQUES FOR SiM3L1XX DEVICES

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Manufacturer	SILABS [Silicon Laboratories]

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AN725

Rev. 0.1

9

Table 2. SiM3L1xx Power Modes

Mode

Description

Mode Entrance

Mode Exit

Normal

 Core operating at full speed

 Code executing from flash

Power Mode 1

(PM1)

 Core operating at full speed

 Code executing from RAM

Execute code from RAM

Jump to code in flash

Power Mode 2

(PM2)

 Core halted

 AHB and APB operate at full

speed for peripherals

WFI or WFE instruction

NVIC or WIC wakeup

Power Mode 3

Fast Wake

(PM3FW)

 All clocks stopped except LFOSC0

or RTC0TCLK

 AHB and APB set to Low Power

Oscillator

 Core clock set to LFOSC0 or

RTC0TCLK

 DMACTRL0 disabled

 Fast wake mode

enabled in PM3CN

 AHB switched to Low

Power Oscillator

 WFI or WFE instruction

Requires a wake up

source or reset defined by

the PMU

Power Mode 3

(PM3)

All clocks stopped

 DMACTRL0 disabled

 Clocks disabled in

PM3CN

 WFI or WFE instruction

Requires a wake up

source or reset defined by

the PMU

Power Mode 4

(PM4)

 Core operating at slower speed

 Code executing from flash

 Set the AHB clock to a

slower source

Set the AHB clock to a

faster source

Power Mode 5

(PM5)

 Core operating at slower speed

 Code executing from RAM

 Set the AHB clock to a

slower source

 Execute code from RAM

Set the AHB clock to a

faster source or jump to

code in flash

Power Mode 6

(PM6)

 Core halted

 AHB and APB operate at a slower

speed for peripherals

 Set the AHB clock to a

slower source

 WFI or WFE instruction

NVIC or WIC wakeup

Power Mode 8

(PM8)

 Low power sleep

 The LDO regulators are disabled

and all active circuitry operates

directly from VBAT

 The following functions are

available: ACCTR0, RTC0, UART0

running from RTC0TCLK,

LPTIMER0, port match, and the

LCD controller

 Register state retention

 SLEEPDEEP set in the

ARM System Control

Register

 WFI or WFE instruction

Requires a wake up

source or reset defined by

the PMU

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