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CXK5T16100TM- Datasheet(PDF) 5 Page - Sony Corporation |
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CXK5T16100TM- Datasheet(HTML) 5 Page - Sony Corporation |
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– 5 – CXK5T16100TM Write cycle time Address valid to end of write Chip enable to end of write Byte enable to end of write Data to write time overlap Data hold from write time Write pulse width Address setup time Write recovery time (WE) Write recovery time (CE, UB, LB) Output active from end of write Write to output in high Z Item VCC = 2.7 to 3.6V tRC tAA tCO tBO tOE tOH tLZ tOLZ tBLZ tHZ∗1 tOHZ∗1 tBHZ∗1 120 — — — — 10 10 5 5 — — — — 120 120 60 60 — — — — 40 35 35 ns ns ns ns ns ns ns ns ns ns ns ns Read cycle time Address access time Chip enable access time (CE) Byte enable access time (UB, LB) Output enable to output valid Output hold from address change Chip enable to output in low Z (CE) Output enable to output in low Z (OE) Byte enable to output in low Z (UB, LB) Chip disable to output in high Z (CE) Chip disable to output in high Z (OE) Byte disable to output in high Z (UB, LB) • Read cycle (WE = “H”) ∗1 t HZ , tOHZ and tBHZ are defined as the time required for outputs to turn to high impedance state and are not referred to as output voltage levels. Min. Max. VCC = 3.3V ± 0.3V 100 — — — — 10 10 5 5 — — — — 100 100 50 50 — — — — 40 35 35 Min. Max. Unit Symbol • Write cycle ∗2 t WHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as output voltage levels. Item VCC = 2.7 to 3.6V tWC tAW tCW tBW tDW tDH tWP tAS tWR tWR1 tOW tWHZ∗2 120 100 100 100 50 0 70 0 5 5 5 — — — — — — — — — — — — 40 ns ns ns ns ns ns ns ns ns ns ns ns Min. Max. VCC = 3.3V ± 0.3V 100 80 80 80 40 0 70 0 5 5 5 — — — — — — — — — — — — 40 Min. Max. Unit Symbol |
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