– 5 –

CXK58512TM/M

Item

Symbol

Min.

Max.

Min.

Max.

-55LL

-70LL

Unit

55

—

—

—

—

15

10

5

—

—

—

55

55

55

30

—

—

—

25

25

70

—

—

—

—

15

10

5

—

—

Min.

Max.

-10LL

100

—

—

—

—

15

10

5

—

—

—

70

70

70

40

—

—

—

25

25

—

100

100

100

50

—

—

—

35

35

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Read cycle time

Address access time

Chip enable access time (CE1)

Chip enable access time (CE2)

Output enable to output valid

Output hold from address change

Chip enable to output in low Z (CE1, CE2)

Output enable to output in low Z (OE)

Chip disable to output in high Z (CE1, CE2)

Output disable to output in high Z (OE)

• Read cycle (WE = "H")

∗ t

HZ1

referred to as output voltage levels.

∗ t

WHZ

is defined as the time required for outputs to turn to high impedance state and is not referred to as

output voltage level.

Item

Symbol

Min.

Max.

Min.

Max.

-55LL

-70LL

Unit

55

50

50

25

0

40

0

0

0

10

—

—

—

—

—

—

—

—

—

—

—

25

70

60

60

30

0

50

0

0

0

10

—

—

—

—

—

—

—

—

—

—

—

25

Min.

Max.

-10LL

100

70

70

40

0

70

0

0

0

10

—

—

—

—

—

—

—

—

—

—

—

30

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

Write cycle time

Address valid to end of write

Chip enable to end of write

Data to write time overlap

Data hold from write time

Write pulse width

Address setup time

Write recovery time (WE)

Write recovery time (CE1, CE2)

Output active from end of write

Write to output in high Z

• Write cycle

(Vcc = 5V ± 10%, GND = 0V, Ta = 0 to +70°C)

(Vcc = 5V ± 10%, GND = 0V, Ta = 0 to +70°C)