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STLC3055N Datasheet(PDF) 6 Page - STMicroelectronics |
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STLC3055N Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 34 page Pin description STLC3055N 6/34 2 Pin description Figure 2. Pin connection (top view) 1 2 3 5 6 4 7 8 9 10 17 11 18 19 20 21 22 44 43 42 41 39 40 38 37 36 35 34 28 27 26 24 23 25 33 32 31 29 30 N.C. GAIN SET PD D1 D0 D2 CTTX2 CTTX1 CKTTX N.C. DET RLIM AGND CVCC RSENSE GATE VPOS CSVR ILTF RD IREF RTH D00TL488-MOD 12 13 14 15 16 Table 2. Pin description N° Pin Function 1 D0 Control Interface: input bit 0. 2 D1 Control Interface: input bit 1. 3 D2 Control interface: input bit 2. 4 PD Power down input. Normally connected to CVCC (or to logic level high). 5 Gain SET Control gain interface: 0 Level Rxgain = 0dB Txgain = -6dB 1 Level Rxgain = +6dB Txgain = -12dB 6,7,36, 38,39,40,42 NC Not connected. 8 DET Logic interface output of the supervision detector (active low). 9 CKTTX Metering pulse clock input (12 KHz or 16KHz square wave). 10 CTTX1 Metering burst shaping external capacitor. 11 CTTX2 Metering burst shaping external capacitor. 12 RTTX Metering pulse cancellation buffer output. TTX filter network should be connected to this point. If not used should be left open. 13 FTTX Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering. 14 RX 4 wire input port (RX input). A 100 k Ω external resistor must be connected to AGND to bias the input stage. This signal is referred to AGND. If connected to single supply CODEC output it must be DC decoupled with proper capacitor. 15 ZAC1 RX buffer output, (the AC impedance is connected from this node to ZAC). 16 ZAC AC impedance synthesis. |
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