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M2S025TS-1VFG144YES Datasheet(PDF) 16 Page - Microsemi Corporation

Part No. M2S025TS-1VFG144YES
Description  SmartFusion2 System-on-Chip FPGAs
Download  156 Pages
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Manufacturer  MICROSEMI [Microsemi Corporation]
Direct Link  http://www.microsemi.com
Logo MICROSEMI - Microsemi Corporation

M2S025TS-1VFG144YES Datasheet(HTML) 16 Page - Microsemi Corporation

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SmartFusion2 Device Family Overview
1- 8
R e v ision 0
Clock Sources: On-Chip Oscillators, PLLs, and CCCs
SmartFusion2 devices have two on-chip RC oscillators—a 1 MHz RC oscillator and a 50 MHz RC
oscillator—and up to two main crystal oscillators (32 KHz–20 MHz). These are available to the user for
generating clocks to the on-chip resources and the logic built on the FPGA fabric array. The second
crystal oscillator available on the SmartFusion2 devices is dedicated for RTC clocking. These oscillators
(except the RTC crystal oscillator) can be used in conjunction with the integrated user phase-locked
loops (PLLs) and FAB_CCCs to generate clocks of varying frequency and phase. In addition to being
available to the user, these oscillators are also used by the system controller, power-on reset circuitry,
MSS during Flash*Freeze mode, and the RTC.
SmartFusion2 devices have up to eight fabric CCC (FAB_CCC) blocks and a dedicated PLL associated
with each CCC to provide flexible clocking to the FPGA fabric portion of the device. The user has the
freedom to use any of the eight PLLs and CCCs to generate the fabric clocks and the internal MSS clock
from the base fabric clock (CLK_BASE). There is also a dedicated CCC block for the MSS (MSS_CCC)
and an associated PLL (MPLL) for MSS clocking and de-skewing the CLK_BASE clock. The fabric
alignment clock controller (FACC), part of the MSS CCC, is responsible for generating various aligned
clocks required by the MSS for correct operation of the MSS blocks and synchornous communication
with the user logic in the FPGA fabric.
High Speed Serial Interfaces
SERDES Interface
SmartFusion2 has up to four 5 Gbps SERDES transceivers, each supporting the following:
4 SERDES/PCS lanes
The native SERDES interface facilitates implementation of Serial RapidIO (SRIO) in fabric or an
SGMII interface for the Ethernet MAC in MSS
PCI Express (PCIe)
PCIe is a high speed, packet-based, point-to-point, low pin count, serial interconnect bus. The
SmartFusion2 family has two hard high-speed serial interface blocks. Each SERDES block contains a
PCIe (PCI Express) system block. The PCIe system is connected to the SERDES block and following
are the main features supported:
Supports x1, x2 and x4 lane configuration
Endpoint configuration only
PCI Express Base Specification Revision 2.0
2.5 and 5.0 Gbps compliant
Embedded Receive (2 KB), Transmit (1 KB) and Retry (1 KB) buffer dual-port RAM
implementation
256 bytes maximum payload size
64-bit AXI or 32-bit/64-bit AHBL Master and Slave interface to the application layer
32-bit APB interface to access configuration and status registers of PCIe system
Up to 3 x 64 bit base address registers
1 virtual channel (VC)
Intel’s PIPE interface (8-bit/16-bit) to interface between the PHY MAC and PHY (SERDES)
Fully compliant PHY PCS sub-layer (125/250 MHz)
XAUI/XGXS Extension
The XAUI/XGXS extension allows the user to implement a 10 Gbps (XGMII) Ethernet PHY interface by
connecting the Ethernet MAC fabric interface through an appropriate soft IP block in the fabric.


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