M2S025TS-1VFG144YES datasheet(40/156 Pages) MICROSEMI | SmartFusion2 System-on-Chip FPGAs

Part No.	M2S025TS-1VFG144YES

Description	SmartFusion2 System-on-Chip FPGAs

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Manufacturer	MICROSEMI [Microsemi Corporation]

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SmartFusion2 DC and Switching Characteristics

2- 22

R e visio n 0

ADVANCE INFORMATION (Subject to Change)

Single-Ended I/O Standards

Low Voltage Complementary Metal Oxide Semiconductor (LVCMOS)

LVCMOS is a widely used switching standard implemented in CMOS transistors. This standard is defined

by JEDEC (JESD 8-5). The LVCMOS standards supported in SmartFusion2 SoC FPGAs are

LVCMOS12, LVCMOS15, LVCMOS18, and LVCMOS25 and LVCMOS33.

3.3 V LVCMOS/LVTTL

LVCMOS 3.3 V or Low-Voltage Transistor-Transistor Logic (LVTTL) is a general standard for 3.3 V

applications.

Minimum and Maximum DC/AC Input and Output Levels Specification

Table 2-18 • LVTTL/LVCMOS 3.3 V DC Voltage Specification

Symbol

Parameters

Conditions

Min.

Typ.

Max.

Units

Notes

Recommended DC Operating Conditions

VDDI

Supply voltage

3.15

3.3

3.45

V

LVTTL/LVCMOS 3.3 V DC Input Voltage Specification

VIH (DC) DC input logic High

2.0

–

3.45

V

VIL (DC) DC input logic Low

–0.3

–

0.8

V

IIH (DC)

Input current High

–

10

mA

IIL (DC)

Input current Low

–

10

mA

LVCMOS 3.3 V DC Output Voltage Specification

VOH

DC output logic High

VDDI – 0.4

–

V

1

VOL

DC output logic Low

–

0.4

V

1

LVTTL 3.3 V DC Output Voltage Specification

VOH

DC output logic High

0.4

–

V

VOL

DC output logic Low

–

2.4

V

LVTTL/LVCMOS 3.3 V AC Specifications

Fmax

Maximum data rate

(for MSIO I/O bank)

AC loading: 10 pF / 500 Ohm Load,

maximum drive/slew

–

600

Mbps

LVTTL/LVCMOS 3.3 V AC Test Parameters Specifications

Vtrip

Measuring/trip point for data path

–

1.4

–

V

Rent

Resistance for enable path (tZH, tZL, tHZ, tLZ)

–

2K

–

Ohms

Cent

Capacitive loading for enable path (tZH, tZL, tHZ, tLZ)

–

5

–

pF

Cload

Capacitive loading for data path (tDP)

–

5

–

pF

Notes:

1. The VOH/VOL test points selected ensure compliance with LVCMOS 3.3 V JESD8-B requirements.

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