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M2S025TS-1FGG144YES Datasheet(PDF) 67 Page - Microsemi Corporation |
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M2S025TS-1FGG144YES Datasheet(HTML) 67 Page - Microsemi Corporation |
67 / 156 page SmartFusion2 System-on-Chip FPGAs R e visio n 0 2 - 49 ADVANCE INFORMATION (Subject to Change) Stub-Series Terminated Logic 1.5 V (SSTL15) SSTL15 Class I and Class II are supported in SmartFusion2 devices, and also comply with the reduced and full drive double data rate (DDR3) standard. SmartFusion2 FPGA I/O supports both standards for single-ended signaling and differential signaling for SSTL18. This standard requires a differential amplifier input buffer and a push-pull output buffer. Minimum and Maximum DC/AC Input and Output Levels Specification Table 2-50 • SSTL15 DC Voltage Specification (for DDRIO I/O Bank Only) Symbols Parameters Conditions Min. Typ. Max. Units Notes Recommended DC Operating Conditions VDDI Supply Voltage 1.425 1.5 1.575 V VTT Termination Voltage 0.698 0.750 0.803 V VREF Input Reference Voltage 0.698 0.750 0.803 V SSTL15 DC Input Voltage Specification VIH(DC) DC input logic High VREF + 0.1 – 1.575 V VIL(DC) DC input logic Low –0.3 – VREF – 0.1 V IIH (DC) Input current High – – 10 µA IIL (DC) Input current Low – – 10 µA SSTL15 DC Output Voltage Specification DDR3/SSTL15 Class I (DDR3 Reduced Drive) VOH DC output logic High 0.8 * VDDI – – V VOL DC output logic Low – – 0.2 * VDDI V IOH at VOH Output minimum source DC current 6.5 – – mA IOL at VOL Output minimum sink current –6.5 – – mA SSTL15 Class II (DDR3 Full Drive) VOH DC output logic High 0.8 * VDDI – – V VOL DC output logic Low – - 0.2 * VDDI V IOH at VOH Output minimum source DC current 7.6 – – mA IOL at VOL Output minimum sink current –7.6 – – mA SSTL15 Differential Voltage Specification VID (DC) DC input differential voltage 0.2 – – V VDIFF (AC) AC input differential voltage 0.7 – – V Vx (AC) AC differential cross point voltage 0.5 * VDDI – 0.150 –0.5 * VDDI + 0.150 V |
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