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TDA7590 Datasheet(PDF) 8 Page - STMicroelectronics |
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TDA7590 Datasheet(HTML) 8 Page - STMicroelectronics |
8 / 42 page Pin description TDA7590 8/42 2.2 Pin function Table 2. Pin function N° Name Type Description 1 SRD1/TI02 I/O Serial receive data. Serial input data for receiver. Timer 2 input/output. 2 STD1 I/O Serial transmit data. Serial output data from transmitter. 3SC02 I/O Serial control 2.Transmitter frame sync only in asynchronous mode, transmitter and receiver frame sync in synchronous mode. 4SC01 I/O Serial control 1. Receive frame sync in asynchronous mode, output from transmitter 2 or serial flag 1 in synchronous mode. 5 DE_N I/O Test data output (input/output). Debug request input and acknowledge output. 6NMI_N I Non-maskable interrupt/ PINIT. Used to enable the PLL during RESET and as a non-maskable interrupt at all other times. 7 SRD0 I/O Serial receive data. Serial input data for receiver. 8 IOVDD I IO power supply. 9 IOVSS I IO ground. 10 STD0 I/O Serial Transmit Data. Serial output data from transmitter. 11 SC10/SCL I/O ESSI1 serial control 0. Receive clock in asynchronous mode, output from transmitter or serial flag in synchronous mode. I2C SCL serial clock line. 12 SC00 I/O Serial control 0. Receive clock in asynchronous mode, output from transmitter 1 or serial flag 0 in synchronous mode. 13 RXD I/O SCI receive data. Receives byte-oriented serial data. 14 TXD I/O SCI read enable. Transmits serial data from SCI transmit shift register. 15 SCLK I/O SCI serial clock. Input or output clock from which data is transferred in synchronous mode and from which the transmit and/or receive baud rate is derived in asynchronous mode. 16 SCK1/TI01 I/O Serial clock. Serial bit clock for transmitter only in asynchronous mode, serial bit clock for both receiver and transmitter in synchronous mode. Timer 1 input/output. 17 SCK0 I/O Serial clock. Serial bit clock for transmitter only in asynchronous mode, serial bit clock for both receiver and transmitter in synchronous mode. 18 RESETN I System reset. A low level applied to RESET_N input initializes the IC. 19 SCANEN I SCAN enable. When active with TESTEN also active, controls the shifting of the internal scan chains. 20 TESTEN I Test enable. When active, puts the chip into test mode and muxes the XTI clock to all flip-flops. When SCANEN is also active, the scan chain shifting is enabled. 21 COREVSS I Core ground. 22 COREVDD I Core power supply. 23 TIO0 I/O Timer 0 input/output. 24 VSSSUB I Analog substrate isolation. |
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